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/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvplan-printing-outer-loop.ll17 ; CHECK-NEXT: EMIT ir<%gep.1> = getelementptr ir<@arr2> ir<0> ir<%outer.iv>
18 ; CHECK-NEXT: EMIT store ir<%outer.iv> ir<%gep.1>
19 ; CHECK-NEXT: EMIT ir<%add> = add ir<%outer.iv> ir<%n>
25 ; CHECK-NEXT: EMIT ir<%gep.2> = getelementptr ir<@arr> ir<0> ir<%inner.iv> ir<%outer.iv>
26 ; CHECK-NEXT: EMIT store ir<%add> ir<%gep.2>
27 ; CHECK-NEXT: EMIT ir<%inner.iv.next> = add ir<%inner.iv> ir<1>
28 ; CHECK-NEXT: EMIT ir<%inner.ec> = icmp ir<%inner.iv.next> ir<8>
29 ; CHECK-NEXT: EMIT branch-on-cond ir<%inner.ec>
35 ; CHECK-NEXT: EMIT ir<%outer.iv.next> = add ir<%outer.iv> ir<1>
36 ; CHECK-NEXT: EMIT ir<%outer.ec> = icmp ir<%outer.iv.next> ir<8>
[all …]
H A Dvplan-sink-scalars-and-merge.ll23 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
90 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
169 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
250 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
261 ; CHECK-NEXT: EMIT vp<[[NOT2:%.+]]> = not ir<%cmp>
325 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
357 ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.1>
426 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
459 ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.0>
577 ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%c.0>
[all …]
H A Dfirst-order-recurrence-sink-replicate-region.ll21 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
25 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
68 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
69 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
109 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
113 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
184 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
261 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
265 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
357 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
[all …]
H A Dvplan-printing.ll19 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
65 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
116 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
161 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
205 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
233 ; CHECK-NEXT: EMIT vp<[[NOT:%.+]]> = not ir<%cmp>
284 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
350 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
400 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
437 ; CHECK-NEXT: EMIT vp<[[NOT2:%.+]]> = not ir<%cmp2>
[all …]
H A Dinterleave-and-scalarize-only.ll15 ; DBG-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
20 ; DBG-NEXT: EMIT vp<[[INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
21 ; DBG-NEXT: EMIT branch-on-count vp<[[INC]]> vp<[[VEC_TC]]>
71 ; DBG-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
104 ; DBG-NEXT: EMIT vp<[[CAN_IV_INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
105 ; DBG-NEXT: EMIT branch-on-count vp<[[CAN_IV_INC]]> vp<[[VEC_TC]]>
184 ; DBG-NEXT: EMIT vp<%2> = CANONICAL-INDUCTION
187 ; DBG-NEXT: EMIT vp<%5> = first-order splice ir<%for> vp<%4>
189 ; DBG-NEXT: EMIT vp<%7> = VF * UF +(nuw) vp<%2>
190 ; DBG-NEXT: EMIT branch-on-count vp<%7> vp<%1>
H A Dicmp-uniforms.ll49 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
52 ; CHECK-NEXT: EMIT vp<[[COND:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
73 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
74 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
H A Dvplan-dot-printing.ll25 ; CHECK-NEXT: " EMIT vp\<[[CAN_IV:%.+]]\> = CANONICAL-INDUCTION\l" +
32 ; CHECK-NEXT: " EMIT vp\<[[CAN_IV_NEXT:%.+]]\> = VF * UF +(nuw) vp\<[[CAN_IV]]\>\l" +
33 ; CHECK-NEXT: " EMIT branch-on-count vp\<[[CAN_IV_NEXT]]\> vp\<{{.+}}\>\l" +
H A Dvplan-sink-scalars-and-merge-vf1.ll18 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
47 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
48 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
/llvm-project-15.0.7/llvm/unittests/Transforms/Vectorize/
H A DVPlanHCFGTest.cpp117 " EMIT ir\<%arr.idx\> = getelementptr ir\<%A\> ir\<%indvars.iv\>\l" + in TEST_F()
118 " EMIT ir\<%l1\> = load ir\<%arr.idx\>\l" + in TEST_F()
119 " EMIT ir\<%res\> = add ir\<%l1\> ir\<10\>\l" + in TEST_F()
120 " EMIT store ir\<%res\> ir\<%arr.idx\>\l" + in TEST_F()
121 " EMIT ir\<%indvars.iv.next\> = add ir\<%indvars.iv\> ir\<1\>\l" + in TEST_F()
122 " EMIT ir\<%exitcond\> = icmp ir\<%indvars.iv.next\> ir\<%N\>\l" + in TEST_F()
123 " EMIT branch-on-cond ir\<%exitcond\>\l" + in TEST_F()
H A DVPlanTest.cpp712 " EMIT vp\<%1\> = add\l" + in TEST()
713 " EMIT vp\<%2\> = sub vp\<%1\>\l" + in TEST()
714 " EMIT br vp\<%1\> vp\<%2\>\l" + in TEST()
720 " EMIT vp\<%4\> = mul vp\<%2\> vp\<%1\>\l" + in TEST()
721 " EMIT ret vp\<%4\>\l" + in TEST()
/llvm-project-15.0.7/llvm/lib/Support/
H A Dregcomp.c357 EMIT(OEND, 0); in llvm_regcomp()
365 EMIT(OEND, 0); in llvm_regcomp()
480 EMIT(OBOL, 0); in p_ere_exp()
486 EMIT(OEOL, 0); in p_ere_exp()
502 EMIT(OANY, 0); in p_ere_exp()
638 EMIT(OBOL, 0); in p_bre()
648 EMIT(OEOL, 0); in p_bre()
684 EMIT(OANY, 0); in p_simp_re()
805 EMIT(OBOW, 0); in p_bracket()
810 EMIT(OEOW, 0); in p_bracket()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-tail-folding-forced.ll14 ; VPLANS-NEXT: EMIT vp<%2> = VF * Part + ir<0>
15 ; VPLANS-NEXT: EMIT vp<%3> = active lane mask vp<%2> <badref>
20 ; VPLANS-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION
25 ; VPLANS-NEXT: EMIT vp<%8> = VF * UF + vp<%4>
26 ; VPLANS-NEXT: EMIT vp<%9> = VF * Part + vp<%8>
27 ; VPLANS-NEXT: EMIT vp<%10> = active lane mask vp<%9> <badref>
28 ; VPLANS-NEXT: EMIT vp<%11> = not vp<%10>
29 ; VPLANS-NEXT: EMIT branch-on-cond vp<%11>
H A Dsve-widen-gep.ll19 ; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
20 ; CHECK-NEXT: EMIT ir<%ptr.iv.1> = WIDEN-POINTER-INDUCTION ir<%start.1>, 1
21 ; CHECK-NEXT: EMIT ir<%ptr.iv.2> = WIDEN-POINTER-INDUCTION ir<%start.2>, 1
27 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
28 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dno-odd-spreg.ll2 ; RUN: | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT
6 ; RUN: | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT
10 ; RUN: | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-EMIT
14 ; ODDSPREG-EMIT: .module oddspreg
15 ; ODDSPREG-NO-EMIT-NOT: .module oddspreg
/llvm-project-15.0.7/llvm/test/Transforms/GCOVProfiling/
H A Dmodules.ll1 ; RUN: opt -passes=insert-gcov-profiling -o - < %s | llvm-dis | FileCheck -check-prefix=EMIT-ARCS %s
3 ; EMIT-ARCS-NOT: call void @llvm_gcda_start_file
/llvm-project-15.0.7/clang/test/ASTMerge/APValue/
H A DAPValue.cpp6 #ifndef EMIT
7 #define EMIT macro
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Driscv-vector-reverse.ll59 ; CHECK-NEXT: EMIT vp<%3> = CANONICAL-INDUCTION
68 ; CHECK-NEXT: EMIT vp<%11> = VF * UF +(nuw) vp<%3>
69 ; CHECK-NEXT: EMIT branch-on-count vp<%11> vp<%2>
190 ; CHECK-NEXT: EMIT vp<%3> = CANONICAL-INDUCTION
199 ; CHECK-NEXT: EMIT vp<%11> = VF * UF +(nuw) vp<%3>
200 ; CHECK-NEXT: EMIT branch-on-count vp<%11> vp<%2>