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/llvm-project-15.0.7/llvm/lib/Support/
H A DHost.cpp1086 if ((EDX >> 15) & 1) in getAvailableFeatures()
1088 if ((EDX >> 23) & 1) in getAvailableFeatures()
1090 if ((EDX >> 25) & 1) in getAvailableFeatures()
1092 if ((EDX >> 26) & 1) in getAvailableFeatures()
1207 if (HasExtLeaf1 && ((EDX >> 29) & 1)) in getAvailableFeatures()
1672 Features["cx8"] = (EDX >> 8) & 1; in getHostCPUFeatures()
1673 Features["cmov"] = (EDX >> 15) & 1; in getHostCPUFeatures()
1674 Features["mmx"] = (EDX >> 23) & 1; in getHostCPUFeatures()
1675 Features["fxsr"] = (EDX >> 24) & 1; in getHostCPUFeatures()
1676 Features["sse"] = (EDX >> 25) & 1; in getHostCPUFeatures()
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/
H A Dcpu_model.c608 if ((EDX >> 15) & 1) in getAvailableFeatures()
610 if ((EDX >> 23) & 1) in getAvailableFeatures()
612 if ((EDX >> 25) & 1) in getAvailableFeatures()
614 if ((EDX >> 26) & 1) in getAvailableFeatures()
694 if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save) in getAvailableFeatures()
696 if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save) in getAvailableFeatures()
698 if (HasLeaf7 && ((EDX >> 8) & 1) && HasAVX512Save) in getAvailableFeatures()
707 getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); in getAvailableFeatures()
747 unsigned EAX, EBX, ECX, EDX; in __cpu_indicator_init() local
763 getX86CpuIDAndInfo(1, &EAX, &EBX, &ECX, &EDX); in __cpu_indicator_init()
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-naive-cluster-stabilization.test32 - 'ADD32rr EDX EDX EAX'
35 - 'EDX=0x0'
49 - 'ADD32rr EDX EDX EAX'
52 - 'EDX=0x0'
H A Danalysis-naive-clusterization.test37 - 'ADD32rr EDX EDX EAX'
40 - 'EDX=0x0'
54 - 'ADD32rr EDX EDX EAX'
57 - 'EDX=0x0'
H A Danalysis-cluster-stabilization.test36 - 'ADD32rr EDX EDX EAX'
39 - 'EDX=0x0'
H A Danalysis-epsilons.test33 - 'ADD32rr EDX EDX EAX'
36 - 'EDX=0x0'
H A Danalysis-clustering-algorithms.test151 - 'ROL32ri EDX EDX i_0x1'
168 - 'EDX=0x0'
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A DDynamicCalleeSavedRegisters.ll12 ; In this case we want to see that EDX/ECX values are saved and EDI/ESI are assumed
15 ; So we can be sure that there is no other reason to save EDX/ECX.
17 ; in registers: ESI, EBP, EAX, EDX and ECX.
48 ; in registers: EAX, ECX, EDX, EDI and ESI.
49 ; The result will return in EAX, ECX and EDX.
H A D2008-09-17-inline-asm-1.ll4 ; %0 must not be put in EAX or EDX.
10 ; In the second asm, $0 and $2 must not be put in EDX.
H A D2010-02-23-RematImplicitSubreg.ll9 ; sub-registers %DX and %EDX.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrSystem.td426 let Uses = [EAX, ECX, EDX] in
428 let Defs = [EAX, EDX], Uses = [ECX] in
452 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
535 let Defs = [EDX, EAX], Uses = [ECX] in
538 let Uses = [EDX, EAX, ECX] in
541 [(int_x86_xsetbv ECX, EDX, EAX)]>, PS;
544 let Uses = [EDX, EAX] in {
611 let Defs = [EAX, EDX], Uses = [ECX] in
614 let Uses = [EAX, ECX, EDX] in
616 [(X86wrpkru EAX, EDX, ECX)]>, PS;
[all …]
H A DX86CallingConv.td50 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
227 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
279 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>,
296 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
327 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
409 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,
935 // The first 2 integer arguments are passed in ECX/EDX
938 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
994 // The first 2 integer arguments are passed in ECX/EDX
995 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
[all …]
H A DX86InstrArithmetic.td71 // EAX,EDX = EAX*GR32
97 // EAX,EDX = EAX*[mem32]
117 // EAX,EDX = EAX*GR32
135 // EAX,EDX = EAX*[mem32]
289 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
290 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
304 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
321 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
322 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
336 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
[all …]
H A DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
H A DX86RegisterInfo.td144 def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>;
170 def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>;
421 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
459 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
461 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>;
481 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;
522 def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>;
528 def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>;
H A DX86IndirectThunks.cpp195 ThunkReg = X86::EDX; in populateThunk()
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_x86_64.cpp334 unsigned int EAX, EBX, ECX, EDX; in probeRequiredCPUFeatures() local
339 __asm__ __volatile__("cpuid" : "=a"(EAX), "=b"(EBX), "=c"(ECX), "=d"(EDX) in probeRequiredCPUFeatures()
341 if (!(EDX & (1u << 27))) { in probeRequiredCPUFeatures()
/llvm-project-15.0.7/llvm/include/llvm/Support/Solaris/sys/
H A Dregset.h26 #undef EDX
/llvm-project-15.0.7/llvm/test/tools/llvm-dwarfdump/X86/
H A Ddebug_frame_LLVM_def_cfa_aspace.s7 # CHECK-NEXT: DW_CFA_LLVM_def_aspace_cfa: EDX +0 in addrspace6
/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrInfo.td42 def EDX;
146 def IN8rr : Inst<(ops), "in AL, EDX", 0xEC, RawFrm,
147 [(set AL, (unspec EDX))]>;
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp197 {codeview::RegisterId::EDX, X86::EDX}, in initLLVMToSEHAndCVRegMapping()
759 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
771 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
808 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
844 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
845 return X86::EDX; in getX86SubSuperRegisterOrZero()
880 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
H A DX86MCTargetDesc.h51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h136 ENTRY(EDX) \
154 ENTRY(EDX) \
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Znver2/
H A Dmulx-read-advance.s4 # PR51494: A read-advance on the implicit read of EDX/RDX was missing.
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/Haswell/
H A Dmulx-read-advance.s4 # PR51494: A read-advance on the implicit read of EDX/RDX was missing.

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