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/llvm-project-15.0.7/llvm/lib/Support/
H A DHost.cpp1095 if ((ECX >> 0) & 1) in getAvailableFeatures()
1097 if ((ECX >> 1) & 1) in getAvailableFeatures()
1099 if ((ECX >> 9) & 1) in getAvailableFeatures()
1101 if ((ECX >> 12) & 1) in getAvailableFeatures()
1103 if ((ECX >> 19) & 1) in getAvailableFeatures()
1105 if ((ECX >> 20) & 1) { in getAvailableFeatures()
1109 if ((ECX >> 23) & 1) in getAvailableFeatures()
1111 if ((ECX >> 25) & 1) in getAvailableFeatures()
1114 if ((ECX >> 22) & 1) in getAvailableFeatures()
1172 if (HasLeaf7 && ((ECX >> 8) & 1)) in getAvailableFeatures()
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/
H A Dcpu_model.c617 if ((ECX >> 0) & 1) in getAvailableFeatures()
619 if ((ECX >> 1) & 1) in getAvailableFeatures()
621 if ((ECX >> 9) & 1) in getAvailableFeatures()
623 if ((ECX >> 12) & 1) in getAvailableFeatures()
625 if ((ECX >> 19) & 1) in getAvailableFeatures()
627 if ((ECX >> 20) & 1) in getAvailableFeatures()
629 if ((ECX >> 23) & 1) in getAvailableFeatures()
631 if ((ECX >> 25) & 1) in getAvailableFeatures()
683 if (HasLeaf7 && ((ECX >> 8) & 1)) in getAvailableFeatures()
711 if (HasExtLeaf1 && ((ECX >> 6) & 1)) in getAvailableFeatures()
[all …]
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax.s135 mov ECX, DWORD PTR [4*ECX + _fnan]
527 xchg EAX, ECX
528 xchg ECX, EAX
538 xchg RAX, [ECX]
539 xchg [ECX], RAX
542 xchg AX, [ECX]
543 xchg [ECX], AX
557 test AX, [ECX]
558 test [ECX], AX
559 test AL, [ECX]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A D2008-08-31-EH_RETURN32.ll14 ; CHECK: movl 12(%ebp), %[[ECX:e..]]
16 ; CHECK: movl %[[ECX]], 4(%ebp,%[[EAX]])
28 ; CHECK: movl 12(%ebp), %[[ECX:e..]]
30 ; CHECK: movl %[[ECX]], 4(%ebp,%[[EAX]])
H A DDynamicCalleeSavedRegisters.ll12 ; In this case we want to see that EDX/ECX values are saved and EDI/ESI are assumed
15 ; So we can be sure that there is no other reason to save EDX/ECX.
17 ; in registers: ESI, EBP, EAX, EDX and ECX.
48 ; in registers: EAX, ECX, EDX, EDI and ESI.
49 ; The result will return in EAX, ECX and EDX.
H A Dphysreg-pairs.ll7 ; ECX, EBX, ESI, EDI, EBP, ESP, to the value. There is no wrapping
/llvm-project-15.0.7/llvm/test/tools/llvm-exegesis/X86/
H A Danalysis-naive-clusterization-same-opcode-different-sched-class.test19 - 'XOR32rr ECX ECX EAX'
22 - 'ECX=0x0'
H A Danalysis-clustering-algorithms.test149 - 'ROL32ri ECX ECX i_0x1'
166 - 'ECX=0x0'
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.td50 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
227 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
279 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>,
296 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
896 // The 'nest' parameter, if any, is passed in ECX.
897 CCIfNest<CCAssignToReg<[ECX]>>,
899 // On swifttailcc pass swiftself in ECX.
953 // The first integer argument is passed in ECX
954 CCIfType<[i32], CCAssignToReg<[ECX]>>,
995 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
[all …]
H A DX86SelectionDAGInfo.cpp58 X86::ECX, X86::EAX, X86::EDI}; in EmitTargetCodeForMemset()
124 Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
159 const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX; in emitRepmovs()
272 X86::ECX, X86::ESI, X86::EDI}; in EmitTargetCodeForMemcpy()
H A DX86InstrSVM.td56 let Uses = [EAX, ECX] in
59 let Uses = [RAX, ECX] in
H A DX86InstrSystem.td426 let Uses = [EAX, ECX, EDX] in
428 let Defs = [EAX, EDX], Uses = [ECX] in
431 let Defs = [RAX, RDX], Uses = [ECX] in
452 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
535 let Defs = [EDX, EAX], Uses = [ECX] in
538 let Uses = [EDX, EAX, ECX] in
541 [(int_x86_xsetbv ECX, EDX, EAX)]>, PS;
611 let Defs = [EAX, EDX], Uses = [ECX] in
614 let Uses = [EAX, ECX, EDX] in
616 [(X86wrpkru EAX, EDX, ECX)]>, PS;
[all …]
H A DX86CallingConv.cpp33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs()
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg()
H A DX86RegisterInfo.td145 def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>;
171 def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>;
421 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
459 def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>;
461 def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>;
481 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>;
528 def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>;
529 def GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>;
H A DX86IndirectThunks.cpp193 ThunkReg = X86::ECX; in populateThunk()
H A DX86ScheduleBtVer2.td430 // ## ECX write Latency: 3cy
432 // Register ECX becomes available in 3 cycles. That is because the value of ECX
448 // ## ECX write Latency: 11cy
450 // The value of ECX becomes available only after 11cy from the start of
H A DX86ExpandPseudo.cpp412 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define); in ExpandMI()
414 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX); in ExpandMI()
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Ddwarfdump-debug-loc-simple.test7 CHECK-NEXT: [0x00000000, 0x00000023) ".text": DW_OP_reg1 ECX
18 CHECK-NEXT: (0x00000000, 0x00000023) ".text": DW_OP_reg1 ECX
/llvm-project-15.0.7/llvm/include/llvm/Support/Solaris/sys/
H A Dregset.h25 #undef ECX
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_x86_64.cpp334 unsigned int EAX, EBX, ECX, EDX; in probeRequiredCPUFeatures() local
339 __asm__ __volatile__("cpuid" : "=a"(EAX), "=b"(EBX), "=c"(ECX), "=d"(EDX) in probeRequiredCPUFeatures()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp196 {codeview::RegisterId::ECX, X86::ECX}, in initLLVMToSEHAndCVRegMapping()
761 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
773 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
810 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
846 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
847 return X86::ECX; in getX86SubSuperRegisterOrZero()
882 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: in getX86SubSuperRegisterOrZero()
H A DX86MCTargetDesc.h51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 enumerator
H A DX86WinCOFFTargetStreamer.cpp298 case X86::ECX: OS << "$ecx"; break; in printFPOReg()
/llvm-project-15.0.7/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h135 ENTRY(ECX) \
153 ENTRY(ECX) \
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DTargetTest.cpp173 const unsigned Reg = X86::ECX; in TEST_F()

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