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Searched refs:DstR (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy() local
48 assert(Register::isPhysicalRegister(DstR.Reg)); in interpretAsCopy()
51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
H A DHexagonFrameLowering.cpp1759 Register DstR = MI->getOperand(0).getReg(); in expandCopy() local
1761 if (!Hexagon::ModRegsRegClass.contains(DstR) || in expandCopy()
1767 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR) in expandCopy()
1817 Register DstR = MI->getOperand(0).getReg(); in expandLoadInt() local
1831 BuildMI(B, It, DL, HII.get(TfrOpc), DstR) in expandLoadInt()
1884 Register DstR = MI->getOperand(0).getReg(); in expandLoadVecPred() local
1987 Register DstR = MI->getOperand(0).getReg(); in expandLoadVec2() local
2065 Register DstR = MI->getOperand(0).getReg(); in expandLoadVec() local
2073 BuildMI(B, It, DL, HII.get(LoadOpc), DstR) in expandLoadVec()
2509 Register DstR = MI.getOperand(0).getReg(); in optimizeSpillSlots() local
[all …]
H A DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY() argument
114 EM.insert(std::make_pair(DstR, SrcR)); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonExpandCondsets.cpp216 MachineBasicBlock::iterator At, unsigned DstR,
626 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
645 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR)) in genCondTfrFor()
648 .addReg(DstR, DstState, DstSR) in genCondTfrFor()
653 .addReg(DstR, DstState, DstSR) in genCondTfrFor()
H A DHexagonGenInsert.cpp533 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
674 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
676 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm()
H A DHexagonSplitDouble.cpp1001 Register DstR = MI->getOperand(0).getReg(); in splitInstr() local
1002 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp711 const Register DstR = Dst.getReg(); in processInstructionForSlowLEA() local
714 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) in processInstructionForSlowLEA()
724 const MachineOperand &Src = SrcR1 == DstR ? Index : Base; in processInstructionForSlowLEA()
726 BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src); in processInstructionForSlowLEA()
733 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA()
734 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR) in processInstructionForSlowLEA()