| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCExpandAtomicPseudoInsts.cpp | 107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI() local
110 PairedCopy(TII, MBB, MI, MI.getDebugLoc(), DstHi, DstLo, Hi, Lo); in expandMI()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1299 auto DstLo = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
1348 MIRBuilder.buildExtract({DstLo}, {CASDst}, 0); in legalizeAtomicCmpxchg128()
1373 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
1384 MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandCopyACC() local
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
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| H A D | MipsSEInstrInfo.cpp | 747 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() local
749 LoInst.addReg(DstLo, RegState::Define); in expandPseudoMTLoHi()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1591 Register DstLo = B.buildMul(S32, Src0, Src1).getReg(0); in applyMappingMAD_64_32() local
1594 MRI.setRegBank(DstLo, AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1651 DstLo = B.buildCopy(S32, DstLo).getReg(0); in applyMappingMAD_64_32()
1653 MRI.setRegBank(DstLo, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1671 auto AddLo = B.buildUAddo(S32, CarryType, DstLo, Src2Lo); in applyMappingMAD_64_32()
1672 DstLo = AddLo.getReg(0); in applyMappingMAD_64_32()
1674 MRI.setRegBank(DstLo, DstBank); in applyMappingMAD_64_32()
1697 B.buildMerge(Dst0, {DstLo, DstHi}); in applyMappingMAD_64_32()
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| H A D | AMDGPUInstructionSelector.cpp | 362 Register DstLo = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
366 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo) in selectG_ADD_SUB()
375 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADD_CO_U32_e64), DstLo) in selectG_ADD_SUB()
392 .addReg(DstLo) in selectG_ADD_SUB()
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| H A D | SIInstrInfo.cpp | 1851 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
1878 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
1900 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
1925 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo() local
1930 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstLo) in expandPostRAPseudo()
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| H A D | SIISelLowering.cpp | 4242 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
4249 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in EmitInstrWithCustomInserter()
4263 .addReg(DstLo) in EmitInstrWithCustomInserter()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1989 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo); in expandLoadVec2() local
2005 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
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