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Searched refs:DstInst (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp459 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency() local
465 if (QII->canExecuteInBundle(*SrcInst, *DstInst) && in adjustSchedDependency()
473 if (DstInst->isCopy()) in adjustSchedDependency()
481 if ((DstInst->isRegSequence() || DstInst->isCopy())) { in adjustSchedDependency()
482 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency()
518 if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) && in adjustSchedDependency()
525 Latency = updateLatency(*SrcInst, *DstInst, IsArtificial, Latency); in adjustSchedDependency()
651 MachineInstr &DstInst = *Dst->getInstr(); in isBestZeroLatency() local
657 if (SrcInst.isPHI() || DstInst.isPHI()) in isBestZeroLatency()
660 if (!TII->isToBeScheduledASAP(SrcInst, DstInst) && in isBestZeroLatency()
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H A DHexagonSubtarget.h328 int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMIRYamlMapping.h493 unsigned DstInst;
498 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
499 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
507 YamlIO.mapRequired("dstinst", Sub.DstInst);
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIRParser.cpp442 {Sub.DstInst, Sub.DstOp}, Sub.Subreg); in setupDebugValueTracking()