459   MachineInstr *DstInst = Dst->getInstr();  in adjustSchedDependency()  local
465   if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&  in adjustSchedDependency()
473   if (DstInst->isCopy())  in adjustSchedDependency()
481   if ((DstInst->isRegSequence() || DstInst->isCopy())) {  in adjustSchedDependency()
482     Register DReg = DstInst->getOperand(0).getReg();  in adjustSchedDependency()
518   if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&  in adjustSchedDependency()
525   Latency = updateLatency(*SrcInst, *DstInst, IsArtificial, Latency);  in adjustSchedDependency()
556                                     MachineInstr &DstInst, bool IsArtificial,  in updateLatency()  argument
651   MachineInstr &DstInst = *Dst->getInstr();  in isBestZeroLatency()  local
657   if (SrcInst.isPHI() || DstInst.isPHI())  in isBestZeroLatency()
660   if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&  in isBestZeroLatency()
661       !TII->canExecuteInBundle(SrcInst, DstInst))  in isBestZeroLatency()