| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCExpandAtomicPseudoInsts.cpp | 106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI() local
110 PairedCopy(TII, MBB, MI, MI.getDebugLoc(), DstHi, DstLo, Hi, Lo); in expandMI()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1590 Register DstHi; in applyMappingMAD_64_32() local
1597 DstHi = IsUnsigned ? B.buildUMulH(S32, Src0, Src1).getReg(0) in applyMappingMAD_64_32()
1599 MRI.setRegBank(DstHi, AMDGPU::SGPRRegBank); in applyMappingMAD_64_32()
1607 DstHi = IsUnsigned ? B.buildUMulH(S32, VSrc0, VSrc1).getReg(0) in applyMappingMAD_64_32()
1609 MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1612 DstHi = buildReadFirstLane(B, MRI, DstHi); in applyMappingMAD_64_32()
1652 DstHi = B.buildCopy(S32, DstHi).getReg(0); in applyMappingMAD_64_32()
1654 MRI.setRegBank(DstHi, AMDGPU::VGPRRegBank); in applyMappingMAD_64_32()
1678 DstHi = AddHi.getReg(0); in applyMappingMAD_64_32()
1679 MRI.setRegBank(DstHi, DstBank); in applyMappingMAD_64_32()
[all …]
|
| H A D | AMDGPUInstructionSelector.cpp | 363 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
369 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) in selectG_ADD_SUB()
380 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi) in selectG_ADD_SUB()
394 .addReg(DstHi) in selectG_ADD_SUB()
|
| H A D | SIInstrInfo.cpp | 1852 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
1881 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1903 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1926 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
1933 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DstHi) in expandPostRAPseudo()
|
| H A D | SIISelLowering.cpp | 4243 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
4255 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in EmitInstrWithCustomInserter()
4265 .addReg(DstHi) in EmitInstrWithCustomInserter()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1300 auto DstHi = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
1349 MIRBuilder.buildExtract({DstHi}, {CASDst}, 64); in legalizeAtomicCmpxchg128()
1373 CAS = MIRBuilder.buildInstr(Opcode, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
1384 MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
|
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
|
| H A D | MipsSEInstrInfo.cpp | 748 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
750 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1988 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
2013 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
|