Searched refs:Dst0 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 877 [&](const MachineBasicBlock *Dst0, const MachineBasicBlock *Dst1) { in selectSuccBB() argument
878 return Prob.getEdgeProbability(&B, Dst0) < in selectSuccBB()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 246 MachineOperand &Dst0 = MI->getOperand(0); in updateOperand() local
248 assert(Dst0.isDef() && Dst1.isDef()); in updateOperand()
252 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg()); in updateOperand()
268 Dst0.setReg(NewReg0); in updateOperand()
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| H A D | AMDGPUInstructionSelector.cpp | 916 Register Dst0 = MI.getOperand(0).getReg(); in selectDivScale() local
919 LLT Ty = MRI->getType(Dst0); in selectDivScale()
939 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0) in selectDivScale()
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| H A D | AMDGPURegisterBankInfo.cpp | 1566 Register Dst0 = MI.getOperand(0).getReg(); in applyMappingMAD_64_32() local
1697 B.buildMerge(Dst0, {DstLo, DstHi}); in applyMappingMAD_64_32()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6881 Register Dst0 = MI.getOperand(0).getReg(); in lowerSADDO_SSUBO() local
6887 LLT Ty = MRI.getType(Dst0); in lowerSADDO_SSUBO()
6891 MIRBuilder.buildAdd(Dst0, LHS, RHS); in lowerSADDO_SSUBO()
6893 MIRBuilder.buildSub(Dst0, LHS, RHS); in lowerSADDO_SSUBO()
6906 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); in lowerSADDO_SSUBO()
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