Searched refs:DivOpc (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1918 unsigned DivOpc; in selectDivRem() local
1924 DivOpc = Mips::SDIV; in selectDivRem()
1928 DivOpc = Mips::UDIV; in selectDivRem()
1937 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | BasicTTIImpl.h | 832 unsigned DivOpc = IsSigned ? Instruction::SDiv : Instruction::UDiv; variable
834 DivOpc, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo,
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4540 unsigned DivOpc; in selectRem() local
4546 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr; in selectRem()
4549 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr; in selectRem()
4563 Register QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, Src1Reg); in selectRem()
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 4691 unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV; in PerformREMCombine() local
4697 if (U->getOpcode() == DivOpc && U->getOperand(0) == Num && in PerformREMCombine()
4702 DAG.getNode(DivOpc, DL, VT, Num, Den), in PerformREMCombine()
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 9508 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; in expandREM() local
9517 if (isOperationLegalOrCustom(DivOpc, VT)) { in expandREM()
9519 SDValue Divide = DAG.getNode(DivOpc, dl, VT, Dividend, Divisor); in expandREM()
|