Searched refs:Den (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCodeGenPrepare.cpp | 172 Value *Num, Value *Den,
177 Value *Num, Value *Den,
667 Type *Ty = Den->getType(); in optimizeWithRcp()
727 Type *Ty = Den->getType(); in optimizeWithFDivFast()
791 Value *Den = FDiv.getOperand(1); in visitFDiv() local
921 Den = Builder.CreateTrunc(Den, I32Ty); in expandDivRem24Impl()
929 JQ = Builder.CreateXor(Num, Den); in expandDivRem24Impl()
942 Value *IB = Den; in expandDivRem24Impl()
993 Value *Rem = Builder.CreateMul(Div, Den); in expandDivRem24Impl()
1020 if (Constant *C = dyn_cast<Constant>(Den)) { in divHasSpecialOptimization()
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| H A D | AMDGPULegalizerInfo.h | 123 Register Den) const;
127 Register Den) const;
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| H A D | AMDGPULegalizerInfo.cpp | 3666 Register Den = MI.getOperand(FirstSrcOpIdx + 1).getReg(); in legalizeUnsignedDIV_REM() local
3670 legalizeUnsignedDIV_REM32Impl(B, DstDivReg, DstRemReg, Num, Den); in legalizeUnsignedDIV_REM()
3672 legalizeUnsignedDIV_REM64Impl(B, DstDivReg, DstRemReg, Num, Den); in legalizeUnsignedDIV_REM()
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| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 4694 const SDValue &Den = N->getOperand(1); in PerformREMCombine() local
4698 U->getOperand(1) == Den) { in PerformREMCombine()
4702 DAG.getNode(DivOpc, DL, VT, Num, Den), in PerformREMCombine()
4703 Den)); in PerformREMCombine()
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| /llvm-project-15.0.7/clang/lib/AST/ |
| H A D | ExprConstant.cpp | 14499 APSInt Den = RHS.getComplexIntReal() * RHS.getComplexIntReal() + in VisitBinaryOperator() local
14503 LHS.getComplexIntImag() * RHS.getComplexIntImag()) / Den; in VisitBinaryOperator()
14506 LHS.getComplexIntReal() * RHS.getComplexIntImag()) / Den; in VisitBinaryOperator()
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