Searched refs:DemandedSrc (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1260 SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
1262 if (DemandedSrc) { in SimplifyDemandedBits()
1263 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, in SimplifyDemandedBits()
2453 if (SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( in SimplifyDemandedBits() local
2456 TLO.DAG.getNode(Op.getOpcode(), dl, VT, DemandedSrc, Idx); in SimplifyDemandedBits()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 11409 if (SDValue DemandedSrc = in performCvtF32UByteNCombine() local
11411 return DAG.getNode(N->getOpcode(), SL, MVT::f32, DemandedSrc); in performCvtF32UByteNCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 37093 APInt DemandedSrc = DemandedElts.zextOrTrunc(SrcVT.getVectorNumElements()); in ComputeNumSignBitsForTargetNode() local
37094 unsigned Tmp = DAG.ComputeNumSignBits(Src, DemandedSrc, Depth + 1); in ComputeNumSignBitsForTargetNode()
41080 APInt DemandedSrc = DemandedElts.lshr(ShiftAmt); in SimplifyDemandedVectorEltsForTargetNode() local
41081 if (SimplifyDemandedVectorElts(Src, DemandedSrc, KnownUndef, KnownZero, TLO, in SimplifyDemandedVectorEltsForTargetNode()
41119 APInt DemandedSrc = DemandedElts.shl(ShiftAmt); in SimplifyDemandedVectorEltsForTargetNode() local
41120 if (SimplifyDemandedVectorElts(Src, DemandedSrc, KnownUndef, KnownZero, TLO, in SimplifyDemandedVectorEltsForTargetNode()
41276 APInt DemandedSrc = DemandedElts.zextOrTrunc(SrcVT.getVectorNumElements()); in SimplifyDemandedVectorEltsForTargetNode() local
41278 if (SimplifyDemandedVectorElts(Src, DemandedSrc, SrcUndef, SrcZero, TLO, in SimplifyDemandedVectorEltsForTargetNode()
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