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Searched refs:DemandedBits (Results 1 – 25 of 36) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Analysis/DemandedBits/
H A Dintrinsics.ll3 ; CHECK-DAG: DemandedBits: 0xff000000 for %1 = or i32 %x, 1
5 ; CHECK-DAG: DemandedBits: 0xff for %3 = trunc i32 %2 to i8
14 ; CHECK-DAG: DemandedBits: 0xff000000 for %1 = or i32 %x, 1
16 ; CHECK-DAG: DemandedBits: 0xff for %3 = trunc i32 %2 to i8
29 ; CHECK-DAG: DemandedBits: 0xff for %x2 = or i32 %x, 1
41 ; CHECK-DAG: DemandedBits: 0xff for %x2 = or i33 %x, 1
53 ; CHECK-DAG: DemandedBits: 0xffff for %x2 = or i32 %x, 1
54 ; CHECK-DAG: DemandedBits: 0x0 for %y2 = or i32 %y, 1
65 ; CHECK-DAG: DemandedBits: 0x0 for %x2 = or i33 %x, 1
66 ; CHECK-DAG: DemandedBits: 0xffff for %y2 = or i33 %y, 1
[all …]
H A Dbasic.ll3 ; CHECK-DAG: DemandedBits: 0xff for %1 = add nsw i32 %a, 5
4 ; CHECK-DAG: DemandedBits: 0xff for %3 = trunc i32 %2 to i8
5 ; CHECK-DAG: DemandedBits: 0xff for %2 = mul nsw i32 %1, %b
6 ; CHECK-DAG: DemandedBits: 0x1 for %4 = trunc i32 %2 to i1
7 ; CHECK-DAG: DemandedBits: 0xff for %5 = zext i1 %4 to i8
8 ; CHECK-DAG: DemandedBits: 0xff for %6 = add nsw i8 %3, %5
9 ; CHECK-DAG: DemandedBits: 0xff for %a in %1 = add nsw i32 %a, 5
10 ; CHECK-DAG: DemandedBits: 0xff for 5 in %1 = add nsw i32 %a, 5
11 ; CHECK-DAG: DemandedBits: 0xff for %1 in %2 = mul nsw i32 %1, %b
14 ; CHECK-DAG: DemandedBits: 0x1 for %2 in %4 = trunc i32 %2 to i1
[all …]
H A Dvectors.ll3 ; CHECK-DAG: DemandedBits: 0xff00 for %x = or <2 x i32> %a, zeroinitializer
4 ; CHECK-DAG: DemandedBits: 0xff00 for %y = or <2 x i32> %b, zeroinitializer
5 ; CHECK-DAG: DemandedBits: 0xff00 for %z = or <2 x i32> %x, %y
6 ; CHECK-DAG: DemandedBits: 0xff for %u = lshr <2 x i32> %z, <i32 8, i32 8>
7 ; CHECK-DAG: DemandedBits: 0xff for %r = trunc <2 x i32> %u to <2 x i8>
19 ; CHECK-DAG: DemandedBits: 0xff for %x = or <2 x i32> %a, zeroinitializer
22 ; CHECK-DAG: DemandedBits: 0xffffffff for %u = and i32 %y, 15
23 ; CHECK-DAG: DemandedBits: 0xffffffff for %v = and i32 %z, 240
24 ; CHECK-DAG: DemandedBits: 0xffffffff for %r = or i32 %u, %v
35 ; CHECK-DAG: DemandedBits: 0xff for %x = or i32 %a, 0
[all …]
H A Dvectors-inseltpoison.ll3 ; CHECK-DAG: DemandedBits: 0xff00 for %x = or <2 x i32> %a, zeroinitializer
4 ; CHECK-DAG: DemandedBits: 0xff00 for %y = or <2 x i32> %b, zeroinitializer
5 ; CHECK-DAG: DemandedBits: 0xff00 for %z = or <2 x i32> %x, %y
6 ; CHECK-DAG: DemandedBits: 0xff for %u = lshr <2 x i32> %z, <i32 8, i32 8>
7 ; CHECK-DAG: DemandedBits: 0xff for %r = trunc <2 x i32> %u to <2 x i8>
19 ; CHECK-DAG: DemandedBits: 0xff for %x = or <2 x i32> %a, zeroinitializer
22 ; CHECK-DAG: DemandedBits: 0xffffffff for %u = and i32 %y, 15
23 ; CHECK-DAG: DemandedBits: 0xffffffff for %v = and i32 %z, 240
24 ; CHECK-DAG: DemandedBits: 0xffffffff for %r = or i32 %u, %v
35 ; CHECK-DAG: DemandedBits: 0xff for %x = or i32 %a, 0
[all …]
H A Dadd.ll3 ; CHECK-DAG: DemandedBits: 0x1e for %1 = and i32 %a, 9
4 ; CHECK-DAG: DemandedBits: 0x1a for %2 = and i32 %b, 9
5 ; CHECK-DAG: DemandedBits: 0x1a for %3 = and i32 %c, 13
6 ; CHECK-DAG: DemandedBits: 0x1a for %4 = and i32 %d, 4
7 ; CHECK-DAG: DemandedBits: 0x1a for %5 = or i32 %2, %3
8 ; CHECK-DAG: DemandedBits: 0x1a for %6 = or i32 %4, %5
9 ; CHECK-DAG: DemandedBits: 0x10 for %7 = add i32 %1, %6
10 ; CHECK-DAG: DemandedBits: 0xffffffff for %8 = and i32 %7, 16
/llvm-project-15.0.7/llvm/include/llvm/Analysis/
H A DDemandedBits.h40 class DemandedBits {
42 DemandedBits(Function &F, AssumptionCache &AC, DominatorTree &DT) : in DemandedBits() function
104 mutable Optional<DemandedBits> DB;
117 DemandedBits &getDemandedBits() { return *DB; } in getDemandedBits()
130 using Result = DemandedBits;
134 DemandedBits run(Function &F, FunctionAnalysisManager &AM);
H A DIVDescriptors.h25 class DemandedBits; variable
170 DemandedBits *DB = nullptr, AssumptionCache *AC = nullptr,
180 DemandedBits *DB = nullptr, AssumptionCache *AC = nullptr,
H A DVectorUtils.h282 class DemandedBits; variable
455 DemandedBits &DB,
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DDemandedBits.cpp80 void DemandedBits::determineLiveOperandBits( in determineLiveOperandBits()
324 void DemandedBits::performAnalysis() { in performAnalysis()
437 APInt DemandedBits::getDemandedBits(Instruction *I) { in getDemandedBits()
448 APInt DemandedBits::getDemandedBits(Use *U) { in getDemandedBits()
475 bool DemandedBits::isInstructionDead(Instruction *I) { in isInstructionDead()
482 bool DemandedBits::isUseDead(Use *U) { in isUseDead()
507 void DemandedBits::print(raw_ostream &OS) { in print()
590 APInt DemandedBits::determineLiveOperandBitsAdd(unsigned OperandNo, in determineLiveOperandBitsAdd()
598 APInt DemandedBits::determineLiveOperandBitsSub(unsigned OperandNo, in determineLiveOperandBitsSub()
615 DemandedBits DemandedBitsAnalysis::run(Function &F, in run()
[all …]
H A DCMakeLists.txt55 DemandedBits.cpp
H A DIVDescriptors.cpp96 DemandedBits *DB, in computeRecurrenceType()
218 RecurrenceDescriptor &RedDes, DemandedBits *DB, AssumptionCache *AC, in AddReductionVar()
827 DemandedBits *DB, AssumptionCache *AC, in isReductionPHI()
/llvm-project-15.0.7/llvm/include/llvm/Transforms/Vectorize/
H A DSLPVectorizer.h32 class DemandedBits; variable
69 DemandedBits *DB = nullptr;
78 DominatorTree *DT_, AssumptionCache *AC_, DemandedBits *DB_,
H A DLoopVectorize.h68 class DemandedBits; variable
180 DemandedBits *DB;
195 BlockFrequencyInfo &BFI_, TargetLibraryInfo *TLI_, DemandedBits &DB_,
H A DLoopVectorizationLegality.h39 class DemandedBits; variable
248 LoopVectorizationRequirements *R, LoopVectorizeHints *H, DemandedBits *DB, in LoopVectorizationLegality()
549 DemandedBits *DB;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp526 if (!C.isSubsetOf(DemandedBits)) { in ShrinkDemandedConstant()
798 if (DemandedBits.isSignMask() && in SimplifyMultipleUseDemandedBits()
1083 APInt DemandedBits = OriginalDemandedBits; in SimplifyDemandedBits() local
1357 if ((LHSKnown.Zero & DemandedBits) == in SimplifyDemandedBits()
1578 if ((DemandedBits & C->getAPIntValue()) == (DemandedBits & Ones) && in SimplifyDemandedBits()
1669 if (DemandedBits.isSignMask() && in SimplifyDemandedBits()
1901 if (DemandedBits.isOne()) in SimplifyDemandedBits()
2165 if (DemandedBits.isSignMask()) { in SimplifyDemandedBits()
2395 if (!(HighBits & DemandedBits)) { in SimplifyDemandedBits()
2443 APInt DemandedSrcBits = DemandedBits; in SimplifyDemandedBits()
[all …]
/llvm-project-15.0.7/llvm/unittests/IR/
H A DDemandedBitsTest.cpp57 TestBinOpExhaustive(DemandedBits::determineLiveOperandBitsAdd, in TEST()
62 TestBinOpExhaustive(DemandedBits::determineLiveOperandBitsSub, in TEST()
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DBDCE.cpp44 static void clearAssumptionsOfUsers(Instruction *I, DemandedBits &DB) { in clearAssumptionsOfUsers()
93 static bool bitTrackingDCE(Function &F, DemandedBits &DB) { in bitTrackingDCE()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp205 APInt DemandedBits = APInt(8, 0xFF); in TEST_F() local
207 EXPECT_TRUE(TL.SimplifyDemandedBits(Op, DemandedBits, Known, TLO)); in TEST_F()
228 APInt DemandedBits = APInt(8, 0xFF); in TEST_F() local
230 EXPECT_FALSE(TL.SimplifyDemandedBits(Op, DemandedBits, Known, TLO)); in TEST_F()
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Analysis/
H A DBUILD.gn44 "DemandedBits.cpp",
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3574 bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
3579 bool ShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
3586 const APInt &DemandedBits, in targetShrinkDemandedConstant() argument
3611 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3618 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3625 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3630 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
3637 SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3644 SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
3757 const APInt &DemandedBits,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h1117 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
1149 const APInt &DemandedBits,
1156 SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/X86/
H A Dx86-movmsk.ll7 ; DemandedBits - MOVMSK zeros the upper bits of the result.
87 ; DemandedBits - If we don't use the lower bits then we just return zero.
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h413 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h518 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h513 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,

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