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Searched refs:Defs (Results 1 – 25 of 214) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrSystem.td25 let hasSideEffects = 1, Defs = [CC] in {
33 let Uses = [R2L], Defs = [R2L] in
135 let hasSideEffects = 1, Defs = [CC] in
139 let hasSideEffects = 1, Defs = [CC] in
195 let hasSideEffects = 1, Defs = [CC] in
220 let hasSideEffects = 1, Defs = [CC] in
256 let hasSideEffects = 1, Defs = [CC] in
268 let hasSideEffects = 1, Defs = [CC] in
278 let hasSideEffects = 1, Defs = [CC] in
290 let Defs = [CC] in
[all …]
H A DSystemZInstrHFP.td21 let Defs = [CC] in {
60 let Defs = [CC] in {
71 let Defs = [CC] in {
77 let Defs = [CC] in {
88 let Defs = [CC] in {
95 let Defs = [CC] in {
102 let Defs = [CC] in {
131 let Defs = [CC] in {
142 let Defs = [CC] in {
152 let Defs = [CC] in {
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H A DSystemZInstrDFP.td22 let Uses = [FPC], Defs = [CC] in {
66 let Uses = [FPC], Defs = [CC] in {
78 let Uses = [FPC], Defs = [CC] in {
116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in
145 let Uses = [FPC], Defs = [CC] in {
157 let Uses = [FPC], Defs = [CC] in {
216 let Uses = [FPC], Defs = [CC] in {
222 let Uses = [FPC], Defs = [CC] in {
228 let Defs = [CC] in {
234 let Defs = [CC] in {
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H A DSystemZInstrInfo.td137 let Defs = [CC] in {
195 let Defs = [CC] in {
210 let Defs = [CC] in {
882 let Defs = [CC] in {
892 let Defs = [CC] in {
902 let Defs = [CC] in {
927 let Defs = [CC] in {
1179 let Defs = [CC] in {
1852 let Defs = [CC];
2072 let Defs = [CC] in
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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
165 expandReg(*R++, Defs); in getDefsUses()
175 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
184 BitVector Defs(NR), Uses(NR); in buildMaps() local
188 Defs.reset(); in buildMaps()
190 getDefsUses(&MI, Defs, Uses); in buildMaps()
283 if (!DU.Defs[PR]) in genMuxInBlock()
307 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { in genMuxInBlock()
311 if (CanDown && DU.Defs[SR1]) in genMuxInBlock()
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H A DHexagonPseudo.td85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
182 Defs = [PC, R31, R6, R7, P0] in
334 let Defs = [R29], hasSideEffects = 1 in
381 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
396 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
411 let Defs = [P0] in
414 let Defs = [P0], isExtended = 1, opExtendable = 0 in
417 let Defs = [R14, R15, R28] in
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp63 bool canBundle(const MachineInstr &MI, const RegUse &Defs,
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
170 const RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
230 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
247 RegUse &Defs, RegUse &Uses, in processRegUses() argument
249 if (!canBundle(MI, Defs, Uses)) in processRegUses()
255 collectRegUses(MI, Defs, Uses); in processRegUses()
303 RegUse Defs, Uses; in runOnMachineFunction() local
304 if (!processRegUses(MI, Defs, Uses, RPT)) { in runOnMachineFunction()
322 if (!processRegUses(*Next, Defs, Uses, RPT)) in runOnMachineFunction()
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H A DSIPostRABundler.cpp49 SmallSet<Register, 16> Defs; member in __anonb04bae040111::SIPostRABundler
83 for (Register Def : Defs) in isDependentLoad()
143 assert(Defs.empty()); in runOnMachineFunction()
146 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
158 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
211 Defs.clear(); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS()
106 InsertUsesDefs(LocalDefs, Defs); in INITIALIZE_PASS()
138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument
152 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions() local
209 Defs.clear(); in InsertITInstructions()
211 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
253 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
263 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td98 class Defs<list<Register> Regs> {
99 list<Register> Defs = Regs;
559 Defs<[DSPOutFlag20]>;
567 Defs<[DSPOutFlag20]>;
575 Defs<[DSPOutFlag20]>;
583 Defs<[DSPOutFlag20]>;
599 Defs<[DSPCarry]>;
850 Defs<[DSPCCond]>;
854 Defs<[DSPCCond]>;
905 Defs<[DSPOutFlag23]>;
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H A DMipsDelaySlotFiller.cpp136 BitVector Defs, Uses; member in __anon74b494060111::RegDefsUses
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon74b494060111::MemDefsUses
353 Defs.set(Mips::RA); in init()
359 Defs.reset(Mips::AT); in init()
370 Defs.set(Mips::RA); in setCallerSaved()
371 Defs.set(Mips::RA_64); in setCallerSaved()
385 Defs |= CallerSavedRegs; in setCallerSaved()
398 Defs |= AllocSet.flip(); in setUnallocatableRegs()
426 Defs |= NewDefs; in update()
442 return isRegInSet(Defs, Reg); in checkRegDefsUses()
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H A DMicroMipsDSPInstrInfo.td227 Defs<[DSPOutFlag22]>;
230 Defs<[DSPOutFlag22]>;
233 Defs<[DSPOutFlag22]>;
236 Defs<[DSPOutFlag22]>;
264 Defs<[DSPOutFlag22]>;
299 Defs<[DSPEFI]>;
302 Defs<[DSPPos, DSPEFI]>;
308 Defs<[DSPEFI]>;
310 Defs<[DSPOutFlag23]>;
312 Defs<[DSPOutFlag23]>;
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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp73 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
76 Defs.insert(V); in findAllDefs()
84 if (Defs.insert(Op).second) in findAllDefs()
87 return Defs; in findAllDefs()
222 auto Defs = findAllDefs(U); in runOnUse() local
225 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); })) in runOnUse()
231 for (Value *V : Defs) in runOnUse()
236 for (Value *V : Defs) in runOnUse()
247 for (Value *V : Defs) in runOnUse()
/llvm-project-15.0.7/clang/utils/TableGen/
H A DNeonEmitter.cpp2007 for (auto *Def : Defs) { in genBuiltinsDef()
2041 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
2111 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode()
2198 createIntrinsic(R, Defs); in runHeader()
2201 genBuiltinsDef(OS, Defs); in runHeader()
2376 for (auto *I : Defs) in run()
2414 I = Defs.erase(I); in run()
2485 for (auto *I : Defs) in runFP16()
2523 I = Defs.erase(I); in runFP16()
2562 for (auto *I : Defs) in runBF16()
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H A DRISCVVEmitter.cpp388 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createBuiltins() local
389 createRVVIntrinsics(Defs); in createBuiltins()
398 for (auto &Def : Defs) { in createBuiltins()
419 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createCodeGen() local
420 createRVVIntrinsics(Defs); in createCodeGen()
422 llvm::stable_sort(Defs, [](const std::unique_ptr<RVVIntrinsic> &A, in createCodeGen()
432 RVVIntrinsic *PrevDef = Defs.begin()->get(); in createCodeGen()
433 for (auto &Def : Defs) { in createCodeGen()
464 emitCodeGenSwitchBody(Defs.back().get(), OS); in createCodeGen()
640 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createSema() local
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H A DSveEmitter.cpp1230 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createHeader() local
1233 createIntrinsic(R, Defs); in createHeader()
1240 Defs.begin(), Defs.end(), [](const std::unique_ptr<Intrinsic> &A, in createHeader()
1249 for (auto &I : Defs) { in createHeader()
1293 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createBuiltins() local
1295 createIntrinsic(R, Defs); in createBuiltins()
1304 for (auto &Def : Defs) { in createBuiltins()
1326 createIntrinsic(R, Defs); in createCodeGenMap()
1335 for (auto &Def : Defs) { in createCodeGenMap()
1359 createIntrinsic(R, Defs); in createRangeChecks()
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H A DClangDataCollectorsEmitter.cpp8 const auto &Defs = RK.getClasses(); in EmitClangDataCollectors() local
9 for (const auto &Entry : Defs) { in EmitClangDataCollectors()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp47 Defs[Hexagon::LC0].insert(Unconditional); in init()
51 Defs[Hexagon::LC1].insert(Unconditional); in init()
134 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
189 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
397 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { in checkPredicates()
410 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
538 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly()
616 for (const auto &I : Defs) { in checkRegisters()
619 if (isLoopRegister(R) && Defs.count(R) > 1 && in checkRegisters()
635 if (!HexagonMCInstrInfo::isPredReg(RI, R) && Defs[R].size() > 1) { in checkRegisters()
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveVariables.cpp485 while (!Defs.empty()) { in UpdatePhysRegDefs()
486 Register Reg = Defs.pop_back_val(); in UpdatePhysRegDefs()
553 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
555 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
560 SmallVector<unsigned, 4> Defs; in runOnBlock() local
575 runOnInstr(MI, Defs); in runOnBlock()
608 HandlePhysRegDef(i, nullptr, Defs); in runOnBlock()
837 DenseSet<unsigned> Defs, Kills; in addNewBlock() local
842 Defs.insert(BBI->getOperand(0).getReg()); in addNewBlock()
855 Defs.insert(Op.getReg()); in addNewBlock()
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H A DReachingDefAnalysis.cpp402 InstSet &Defs) const { in getGlobalReachingDefs()
404 Defs.insert(Def); in getGlobalReachingDefs()
409 getLiveOuts(MBB, PhysReg, Defs); in getGlobalReachingDefs()
413 MCRegister PhysReg, InstSet &Defs) const { in getLiveOuts()
415 getLiveOuts(MBB, PhysReg, Defs, VisitedBBs); in getLiveOuts()
419 MCRegister PhysReg, InstSet &Defs, in getLiveOuts() argument
431 Defs.insert(Def); in getLiveOuts()
434 getLiveOuts(Pred, PhysReg, Defs, VisitedBBs); in getLiveOuts()
561 SmallSet<int, 2> Defs; in isSafeToMove() local
567 Defs.insert(MO.getReg()); in isSafeToMove()
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/llvm-project-15.0.7/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp151 if (Defs) { in getPreviousDefInBlock()
156 if (Iter != Defs->rend()) in getPreviousDefInBlock()
177 if (Defs) { in getPreviousDefFromEnd()
179 return &*Defs->rbegin(); in getPreviousDefFromEnd()
258 (void)Defs; in insertUse()
259 assert((!Defs || (++Defs->begin() == Defs->end())) && in insertUse()
478 if (++DefIter != Defs->end()) { in fixupDefs()
498 auto *FirstDef = &*Defs->begin(); in fixupDefs()
874 if (Defs) in applyInsertUpdates()
875 return &*(--Defs->end()); in applyInsertUpdates()
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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrKL.td19 let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
26 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
32 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
39 Defs = [EFLAGS] in {
69 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
H A DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
91 let Defs = [AL] in
94 let Defs = [AX] in
97 let Defs = [EAX] in
474 let Defs = [SSP] in {
479 } // Defs SSP
496 } // Defs SSP
512 let Defs = [SSP] in {
521 } // Defs SSP
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/llvm-project-15.0.7/llvm/test/TableGen/
H A DForeachList.td13 def Defs {
18 foreach i = Defs.a in {
22 foreach i = !listconcat(Defs.a, Defs.b) in
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCTagsEmitter.cpp70 const auto &Defs = Records.getDefs(); in run() local
73 Tags.reserve(Classes.size() + Defs.size()); in run()
79 for (const auto &D : Defs) in run()

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