Searched refs:DIVW (Results 1 – 10 of 10) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | phi-eliminate.mir | 145 ; CHECK: %19:gprc = DIVW %8, %9 163 ; CHECK: %26:gprc = DIVW %19, %9 179 ; CHECK: %28:gprc = DIVW %56, %9 234 %19:gprc = DIVW %8, %9 247 %26:gprc = DIVW %19, %9 260 %28:gprc = DIVW %56, %9
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoM.td | 19 def riscv_divw : SDNode<"RISCVISD::DIVW", SDT_RISCVIntBinOpW>; 55 def DIVW : ALUW_rr<0b0000001, 0b100, "divw">, 88 def : PatGprGpr<riscv_divw, DIVW>;
|
| H A D | RISCVSExtWRemoval.cpp | 102 case RISCV::DIVW: in isAllUsesReadW() 210 case RISCV::DIVW: in isSignExtendingOpW()
|
| H A D | RISCVISelLowering.h | 69 DIVW, enumerator
|
| H A D | RISCVISelDAGToDAG.cpp | 2161 case RISCV::DIVW: in hasAllNBitUsers()
|
| H A D | RISCVISelLowering.cpp | 6794 return RISCVISD::DIVW; in getRISCVWOpcode() 9668 case RISCVISD::DIVW: in ComputeNumSignBitsForTargetNode() 11623 NODE_NAME_CASE(DIVW) in getTargetNodeName()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 945 DIVW, 987 (instregex "DIVW(U)?(O)?_rec$")
|
| H A D | P10InstrResources.td | 481 DIVW,
|
| H A D | PPCInstrInfo.td | 2750 defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
|
| H A D | PPCISelLowering.cpp | 12129 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div) in emitProbedAlloca()
|