| /llvm-project-15.0.7/clang/test/CXX/special/class.inhctor/ |
| H A D | p7.cpp | 43 struct D7 : B5 { struct
45 template<typename T> D7(T, ...);
48 D7 d7(0);
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| /llvm-project-15.0.7/clang/test/CXX/special/class.copy/ |
| H A D | p23-cxx11.cpp | 122 struct D7 { struct
137 template struct CopyAssign<D7>; // expected-note {{here}} argument
138 template struct MoveAssign<D7>; // expected-note {{here}}
139 template struct MoveOrCopyAssign<D7>; // expected-note {{here}}
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| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | AlignOfTest.cpp | 58 struct D7 : S1, S3 {}; struct
162 EXPECT_EQ(alignof(D7), alignof(AlignedCharArrayUnion<D7>)); in TEST()
217 EXPECT_EQ(sizeof(D7), sizeof(AlignedCharArrayUnion<D7>)); in TEST()
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | 2013-04-16-AAPCS-C5-vs-VFP.ll | 30 double %p7, ; --> D7
55 double 23.7, ; --> D7
|
| H A D | 2013-04-16-AAPCS-C4-vs-VFP.ll | 71 double %p7, ; --> D7
90 double 23.7, ; --> D7
|
| H A D | 2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll | 15 double %vfp7, ; --> D7, NSAA=SP
|
| H A D | 2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll | 17 double %vfp7, ; --> D7, NSAA=SP
|
| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | BitsInit.td | 37 bits<1> D7 = { 3 }; // type mismatch. LHS doesn't have enough bits
76 // CHECK: bits<1> D7 = { !cast<bit>(3) };
|
| H A D | ConcatenatedSubregs.td | 58 def D7 : MyReg<"d7", [S14, S15]>;
88 // CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
|
| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | warn-cast-align.cpp | 110 struct D7 : virtual D3 { struct
128 __attribute__((aligned(1))) D7 t10; in test2()
|
| /llvm-project-15.0.7/llvm/test/DebugInfo/PDB/ |
| H A D | dbi-bytes.test | 26 MODI-NEXT: E040: 00000000 01000000 10000000 0A000000 20005060 00000000 347497D7 00000000 |....…
40 SC-NEXT: E14C: 01000000 10000000 0A000000 20005060 00000000 347497D7 00000000 02000000 |......…
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-objdump/COFF/ |
| H A D | eh_frame.test | 12 # CHECK: Augmentation data: 00 D7 25 40 00 00 00
|
| /llvm-project-15.0.7/llvm/test/MC/MachO/ |
| H A D | x86_64-symbols.s | 26 D7: label
|
| H A D | x86_32-symbols.s | 26 D7: label
|
| /llvm-project-15.0.7/llvm/test/CodeGen/M68k/ |
| H A D | reserved-regs.ll | 15 ; RUN: llc -mtriple=m68k -mattr="+reserve-d7" < %s | FileCheck --check-prefix=D7 %s
64 ; D7-NOT: %d7
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/MCTargetDesc/ |
| H A D | M68kBaseInfo.h | 223 return M68k::D7; in getMaskedSpillRegister()
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/fuchsia/ |
| H A D | multiple-inheritance.cpp | 128 struct D7 : V11, V12 {}; struct
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.td | 105 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
107 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
142 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
144 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
216 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
218 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
304 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-bytestring.ll | 4 …BE\BF\C0\C1\C2\C3\C4\C5\C6\C7\C8\C9\CA\CB\CC\CD\CE\CF\D0\D1\D2\D3\D4\D5\D6\D7\D8\D9\DA\DB\DC\DD\DE…
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 78 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
98 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
226 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
246 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
|
| H A D | ARMBaseRegisterInfo.h | 107 case D7: case D6: case D5: case D4: in isARMArea3Register()
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/Disassembler/ |
| H A D | M68kDisassembler.cpp | 37 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
|
| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | X86RecognizableInstr.h | 53 MAP(D7, 87) \
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 232 M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3, in getRegisterByIndex()
241 if (Register >= M68k::D0 && Register <= M68k::D7) in getRegisterIndex()
490 case M68k::D7: in checkRegisterClass()
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kCallingConv.td | 117 def CSR_STD : CalleeSavedRegs<(add D2, D3, D4, D5, D6, D7,
|