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/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DP10InstrResources.td1204 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 0 input operands
1214 // 3 Cycles ALU operations, and 3 Cycles ALU operations, 1 input operands
1256 // 3 Cycles ALU operations, 3 Cycles ALU operations, 3 Cycles ALU operations, and 3 Cycles ALU oper…
1379 // 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load …
1386 // 6 Cycles Load operations, 6 Cycles Load operations, 6 Cycles Load operations, and 6 Cycles Load …
1439 // 6 Cycles Load operations, 4 Cycles ALU2 operations, 3 Cycles Simple Fixed-point (SFX) operations…
1572 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix…
1917 …Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, 3 Cycles ALU operatio…
1925 // 3 Cycles Store operations, 3 Cycles ALU operations, 3 Cycles Store operations, and 3 Cycles Stor…
1933 // 3 Cycles Store operations, 3 Cycles Store operations, 3 Cycles Store operations, and 3 Cycles St…
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp44 unsigned int Cycles = 0; member
48 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
75 unsigned int Cycles = 0);
78 unsigned int &Cycles);
133 unsigned Cycles = ReturnBB.second; in runOnMachineFunction() local
140 if (Cycles < Threshold) { in runOnMachineFunction()
166 if (Cycles >= Threshold) in findReturns()
177 findReturns(Succ, Cycles); in findReturns()
191 Cycles += BBInfo.Cycles; in cyclesUntilReturn()
203 Cycles += CyclesToEnd; in cyclesUntilReturn()
[all …]
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstruction.cpp22 unsigned Cycles) { in writeStartEvent() argument
25 CRD.Cycles = Cycles; in writeStartEvent()
26 DependentWriteCyclesLeft = Cycles; in writeStartEvent()
31 unsigned Cycles) { in writeStartEvent() argument
41 if (TotalCycles < Cycles) { in writeStartEvent()
44 CRD.Cycles = Cycles; in writeStartEvent()
45 TotalCycles = Cycles; in writeStartEvent()
132 if (CriticalRegDep.Cycles) in computeCriticalRegDep()
138 if (WriteCRD.Cycles > MaxLatency) in computeCriticalRegDep()
144 if (ReadCRD.Cycles > MaxLatency) in computeCriticalRegDep()
H A DPipeline.cpp46 ++Cycles; in run()
49 return Cycles; in run()
97 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n'); in notifyCycleBegin()
103 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n"); in notifyCycleEnd()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-mca/X86/
H A DTestIncrementalMCA.cpp47 Expected<unsigned> Cycles = P->run(); in TEST_F() local
48 if (!Cycles) { in TEST_F()
50 ASSERT_TRUE(Cycles.errorIsA<mca::InstStreamPause>()); in TEST_F()
51 llvm::consumeError(Cycles.takeError()); in TEST_F()
57 Expected<unsigned> Cycles = P->run(); in TEST_F() local
58 ASSERT_TRUE(bool(Cycles)); in TEST_F()
148 Expected<unsigned> Cycles = P->run(); in TEST_F() local
149 if (!Cycles) { in TEST_F()
152 llvm::consumeError(Cycles.takeError()); in TEST_F()
158 Expected<unsigned> Cycles = P->run(); in TEST_F() local
[all …]
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCSchedule.h65 uint16_t Cycles; member
68 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
78 int16_t Cycles; member
82 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
97 int Cycles; member
101 && Cycles == Other.Cycles;
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A Dforwarding-A57.s5 # CHECK-NEXT: Total Cycles: 12
12 # CHECK-NEXT: Total Cycles: 13
19 # CHECK-NEXT: Total Cycles: 12
26 # CHECK-NEXT: Total Cycles: 13
33 # CHECK-NEXT: Total Cycles: 16
40 # CHECK-NEXT: Total Cycles: 16
47 # CHECK-NEXT: Total Cycles: 12
54 # CHECK-NEXT: Total Cycles: 12
61 # CHECK-NEXT: Total Cycles: 16
89 # CHECK-NEXT: Total Cycles: 8
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp109 DelayInfo(DelayType Type, unsigned Cycles) { in DelayInfo()
114 VALUCycles = Cycles; in DelayInfo()
118 TRANSCycles = Cycles; in DelayInfo()
123 SALUCycles = Cycles; in DelayInfo()
151 bool advance(DelayType Type, unsigned Cycles) { in advance()
161 VALUCycles -= Cycles; in advance()
174 TRANSCycles -= Cycles; in advance()
178 if (SALUCycles <= Cycles) { in advance()
183 SALUCycles -= Cycles; in advance()
228 if (I->second.advance(Type, Cycles)) in advance()
[all …]
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCSchedule.cpp49 if (WLEntry->Cycles < 0) in computeInstrLatency()
50 return WLEntry->Cycles; in computeInstrLatency()
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles)); in computeInstrLatency()
95 if (!I->Cycles) in getReciprocalThroughput()
98 double Temp = NumUnits * 1.0 / I->Cycles; in getReciprocalThroughput()
163 DelayCycles = std::min(DelayCycles, E.Cycles); in getForwardingDelayCycles()
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/X86/
H A Duop-queue.s19 # BTVER2-DEC-2-NEXT: Total Cycles: 3003
29 # BTVER2-DEC-1-NEXT: Total Cycles: 6003
34 # BTVER2-UOPQ-1-NEXT: Total Cycles: 6003
39 # BTVER2-UOPQ-2-NEXT: Total Cycles: 3003
44 # HASWELL-DEC-2-NEXT: Total Cycles: 3003
49 # HASWELL-UOPQ-1-NEXT: Total Cycles: 6003
54 # HASWELL-UOPQ-2-NEXT: Total Cycles: 3003
59 # HASWELL-UOPQ-3-NEXT: Total Cycles: 2003
64 # HASWELL-UOPQ-4-NEXT: Total Cycles: 1503
H A Dread-after-ld-1.s20 # BARCELONA-NEXT: Total Cycles: 20
23 # BDVER2-NEXT: Total Cycles: 17
26 # BDWELL-NEXT: Total Cycles: 17
29 # BTVER2-NEXT: Total Cycles: 25
32 # HASWELL-NEXT: Total Cycles: 19
35 # SANDY-NEXT: Total Cycles: 20
38 # SKYLAKE-NEXT: Total Cycles: 18
41 # ZNVER1-NEXT: Total Cycles: 20
44 # ZNVER2-NEXT: Total Cycles: 21
47 # ZNVER3-NEXT: Total Cycles: 17
H A Dvariable-blend-read-after-ld-1.s28 # BDVER2-NEXT: Total Cycles: 10
31 # BDWELL-NEXT: Total Cycles: 10
34 # BTVER2-NEXT: Total Cycles: 11
37 # HASWELL-NEXT: Total Cycles: 11
40 # IVY-NEXT: Total Cycles: 11
43 # SANDY-NEXT: Total Cycles: 11
46 # SKYLAKE-NEXT: Total Cycles: 11
49 # ZNVER1-NEXT: Total Cycles: 11
52 # ZNVER2-NEXT: Total Cycles: 11
H A Dvariable-blend-read-after-ld-2.s28 # BDVER2-NEXT: Total Cycles: 10
31 # BDWELL-NEXT: Total Cycles: 10
34 # BTVER2-NEXT: Total Cycles: 11
37 # HASWELL-NEXT: Total Cycles: 11
40 # IVY-NEXT: Total Cycles: 11
43 # SANDY-NEXT: Total Cycles: 11
46 # SKYLAKE-NEXT: Total Cycles: 11
49 # ZNVER1-NEXT: Total Cycles: 11
52 # ZNVER2-NEXT: Total Cycles: 11
H A Dbextr-read-after-ld.s17 # BDVER2-NEXT: Total Cycles: 9
20 # BDWELL-NEXT: Total Cycles: 10
23 # BTVER2-NEXT: Total Cycles: 7
26 # HASWELL-NEXT: Total Cycles: 10
29 # SKYLAKE-NEXT: Total Cycles: 10
32 # ZNVER1-NEXT: Total Cycles: 8
35 # ZNVER2-NEXT: Total Cycles: 8
H A Dbzhi-read-after-ld.s15 # BDWELL-NEXT: Total Cycles: 9
16 # HASWELL-NEXT: Total Cycles: 9
17 # SKYLAKE-NEXT: Total Cycles: 9
18 # ZNVER1-NEXT: Total Cycles: 8
19 # ZNVER2-NEXT: Total Cycles: 8
H A Dfma3-read-after-ld-1.s20 # BDWELL-NEXT: Total Cycles: 13
23 # HASWELL-NEXT: Total Cycles: 14
26 # SKYLAKE-NEXT: Total Cycles: 13
29 # ZNVER1-NEXT: Total Cycles: 15
/llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h122 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); in onGroupIssued() local
123 if (CriticalPredecessor.Cycles < Cycles) { in onGroupIssued()
125 CriticalPredecessor.Cycles = Cycles; in onGroupIssued()
187 if (isWaiting() && CriticalPredecessor.Cycles) in cycleEvent()
188 CriticalPredecessor.Cycles--; in cycleEvent()
/llvm-project-15.0.7/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp22 unsigned Cycles) in TimelineView() argument
24 MaxCycle(Cycles == 0 ? std::numeric_limits<unsigned>::max() : Cycles), in TimelineView()
121 static void tryChangeColor(raw_ostream &OS, unsigned Cycles, in tryChangeColor() argument
126 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize); in tryChangeColor()
257 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { in printTimelineHeader() argument
259 if (Cycles >= 10) { in printTimelineHeader()
261 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
272 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
H A DBottleneckAnalysis.cpp506 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID); in onEvent() local
513 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles); in onEvent()
519 if (RegDep.Cycles) { in onEvent()
520 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID); in onEvent()
522 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
526 if (MemDep.Cycles) { in onEvent()
527 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID); in onEvent()
529 addMemoryDep(From, To, Cycles); in onEvent()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp853 struct Cycles { struct
900 << Cycles{"ResLength", ResLength} in shouldConvertIf()
903 << Cycles{"CritLimit", CritLimit} in shouldConvertIf()
989 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
992 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
994 << Cycles{"CritLimit", CritLimit} << "."; in shouldConvertIf()
1007 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
1013 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
1133 unsigned Cycles = 0; in shouldConvertIf() local
1137 Cycles += NumCycles - 1; in shouldConvertIf()
[all …]
/llvm-project-15.0.7/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp32 unsigned Cycles = Resource.second.size(); in execute() local
41 std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits))); in execute()
56 ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits))); in execute()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.cpp66 Result.push_back({WPR->ProcResourceIdx, WPR->Cycles}); in getNonRedundantWriteProcRes()
67 ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles; in getNonRedundantWriteProcRes()
71 float RemainingCycles = WPR->Cycles; in getNonRedundantWriteProcRes()
188 DensePressure[WPR.ProcResourceIdx] += WPR.Cycles; in computeIdealizedProcResPressure()
194 distributePressure(WPR.Cycles, Subunits, DensePressure); in computeIdealizedProcResPressure()
278 std::max<double>(LatencyMeasure.PerInstructionValue, WLE->Cycles); in getAsPoint()
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp344 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString() local
345 ItinString += " { " + itostr(Cycles) + ", "; in FormItineraryStageString()
991 Cycles.push_back(Cycles[i]); in ExpandProcResources()
1007 Cycles.push_back(Cycles[i]); in ExpandProcResources()
1108 WLEntry.Cycles = 0; in GenSchedClassTables()
1139 std::vector<int64_t> Cycles = in GenSchedClassTables() local
1142 if (Cycles.empty()) { in GenSchedClassTables()
1145 Cycles.resize(PRVec.size(), 1); in GenSchedClassTables()
1164 WPREntry.Cycles = Cycles[PRIdx]; in GenSchedClassTables()
1173 WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles; in GenSchedClassTables()
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Ddirect-branch.s11 # M3-NEXT: Total Cycles: 18
12 # M4-NEXT: Total Cycles: 18
13 # M5-NEXT: Total Cycles: 18
/llvm-project-15.0.7/llvm/include/llvm/MCA/
H A DInstruction.h188 unsigned Cycles; member
303 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
375 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
419 void subtract(unsigned Cycles) { in subtract() argument
420 assert(End >= Cycles); in subtract()
421 End -= Cycles; in subtract()
439 ResourceUsage(CycleSegment Cycles, unsigned Units = 1)
440 : CS(Cycles), NumUnits(Units) {} in CS()

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