112   void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
344     int Cycles = Stage->getValueAsInt("Cycles");  in FormItineraryStageString()  local
345     ItinString += "  { " + itostr(Cycles) + ", ";  in FormItineraryStageString()
969                                            std::vector<int64_t> &Cycles,  in ExpandProcResources()  argument
971   assert(PRVec.size() == Cycles.size() && "failed precondition");  in ExpandProcResources()
991         Cycles.push_back(Cycles[i]);  in ExpandProcResources()
1007         Cycles.push_back(Cycles[i]);  in ExpandProcResources()
1108       WLEntry.Cycles = 0;  in GenSchedClassTables()
1129         WLEntry.Cycles += WriteRes->getValueAsInt("Latency");  in GenSchedClassTables()
1139         std::vector<int64_t> Cycles =  in GenSchedClassTables()  local
1142         if (Cycles.empty()) {  in GenSchedClassTables()
1145           Cycles.resize(PRVec.size(), 1);  in GenSchedClassTables()
1146         } else if (Cycles.size() != PRVec.size()) {  in GenSchedClassTables()
1154                   .concat(Twine(Cycles.size())));  in GenSchedClassTables()
1157         ExpandProcResources(PRVec, Cycles, ProcModel);  in GenSchedClassTables()
1164           WPREntry.Cycles = Cycles[PRIdx];  in GenSchedClassTables()
1173               WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;  in GenSchedClassTables()
1211         RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");  in GenSchedClassTables()
1285        << format("%2d", WPREntry.Cycles) << "}";  in EmitSchedClassTables()
1300     OS << "  {" << format("%2d", WLEntry.Cycles) << ", "  in EmitSchedClassTables()
1318        << format("%2d", RAEntry.Cycles) << "}";  in EmitSchedClassTables()