Searched refs:Const1 (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | f16-imm.ll | 26 define half @Const1() {
27 ; CHECK-FP16-LABEL: Const1:
32 ; CHECK-NOFP16-LABEL: Const1:
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 923 SDValue Const1; in performORCombine() local
926 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); in performORCombine()
2329 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN32() local
2338 Const1); in lowerFCOPYSIGN32()
2342 Const1); in lowerFCOPYSIGN32()
2377 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFCOPYSIGN64() local
2405 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); in lowerFCOPYSIGN64()
2432 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); in lowerFABS32() local
2442 Op.getOperand(0), Const1); in lowerFABS32()
2453 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); in lowerFABS32()
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2899 SDValue Const1 = DAG.getConstant(1, DL, MVT::i64); in lowerEXTRACT_VECTOR_ELT() local
2900 SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2903 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2904 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerEXTRACT_VECTOR_ELT()
2957 SDValue Const1 = DAG.getConstant(1, DL, MVT::i64); in lowerINSERT_VECTOR_ELT() local
2958 SDValue HalfIdx = DAG.getNode(ISD::SRL, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT()
2961 SDValue AndIdx = DAG.getNode(ISD::AND, DL, MVT::i64, {Idx, Const1}); in lowerINSERT_VECTOR_ELT()
2962 SDValue Shift = DAG.getNode(ISD::XOR, DL, MVT::i64, {AndIdx, Const1}); in lowerINSERT_VECTOR_ELT()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 8019 bool Const1 = isa<ConstantInt>(Op1) || isa<ConstantFP>(Op1) || in optimizeInst() local
8021 if (Const0 || Const1) { in optimizeInst()
8022 if (!Const0 || !Const1) { in optimizeInst()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2128 auto Const1 = B.buildConstant(S32, ExpBits); in extractF64Exponent() local
2133 .addUse(Const1.getReg(0)); in extractF64Exponent()
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