Searched refs:CondCycles (Results 1 – 8 of 8) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 115 int CondCycles = 0, TCycles = 0, FCycles = 0; member
524 PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles, in canConvertIf()
936 unsigned CondDepth = adjCycles(BranchDepth, PI.CondCycles); in shouldConvertIf()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 890 int &CondCycles, int &TrueCycles, in canInsertSelect() argument
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 540 Register FalseReg, int &CondCycles, in canInsertSelect() argument
561 CondCycles = 2; in canInsertSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 310 Register TrueReg, Register FalseReg, int &CondCycles,
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| H A D | SIInstrInfo.cpp | 2725 Register FalseReg, int &CondCycles, in canInsertSelect() argument
2736 CondCycles = TrueCycles = FalseCycles = NumInsts; // ??? in canInsertSelect()
2756 CondCycles = TrueCycles = FalseCycles = NumInsts; // ??? in canInsertSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 604 Register FalseReg, int &CondCycles, in canInsertSelect() argument
628 CondCycles = 1 + ExtraCondLat; in canInsertSelect()
641 CondCycles = 5 + ExtraCondLat; in canInsertSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1536 Register FalseReg, int &CondCycles, in canInsertSelect() argument
1569 CondCycles = 1; in canInsertSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3340 Register FalseReg, int &CondCycles, in canInsertSelect() argument
3364 CondCycles = 2; in canInsertSelect()
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