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Searched refs:Cascade (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRegAllocGreedy.h73 unsigned Cascade = 0; member
111 Info[Reg].Cascade = Cascade; in setCascade()
115 unsigned Cascade = getCascade(Reg); in getOrAssignNewCascade() local
116 if (!Cascade) { in getOrAssignNewCascade()
117 Cascade = NextCascade++; in getOrAssignNewCascade()
118 setCascade(Reg, Cascade); in getOrAssignNewCascade()
120 return Cascade; in getOrAssignNewCascade()
124 unsigned Cascade = getCascade(Reg); in getCascadeOrCurrentNext() local
125 if (!Cascade) in getCascadeOrCurrentNext()
126 Cascade = NextCascade; in getCascadeOrCurrentNext()
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H A DRegAllocEvictionAdvisor.cpp201 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in canEvictInterferenceBasedOnCost() local
239 if (Cascade == IntfCascade) in canEvictInterferenceBasedOnCost()
242 if (Cascade < IntfCascade) { in canEvictInterferenceBasedOnCost()
H A DMLRegallocEvictAdvisor.cpp544 unsigned Cascade = RA.getExtraInfo().getCascadeOrCurrentNext(VirtReg.reg()); in loadInterferenceFeatures() local
578 if (Cascade <= IntfCascade) { in loadInterferenceFeatures()
H A DRegAllocGreedy.cpp453 unsigned Cascade = ExtraInfo->getOrAssignNewCascade(VirtReg.reg()); in evictInterference() local
456 << " interference: Cascade " << Cascade << '\n'); in evictInterference()
477 assert((ExtraInfo->getCascade(Intf->reg()) < Cascade || in evictInterference()
480 ExtraInfo->setCascade(Intf->reg(), Cascade); in evictInterference()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dregalloc-advanced-split-cost.ll17 ; CHECK: RS_Split Cascade 1