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Searched refs:CTR (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dppc-passname-assert.ll4 …re=ppc-ctr-loops-verify -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-BEFORE-CTR-LOOPS-VERIFY
5 ; STOP-BEFORE-CTR-LOOPS-VERIFY-NOT: -ppc-ctr-loops-verify
6 ; STOP-BEFORE-CTR-LOOPS-VERIFY-NOT: "ppc-ctr-loops-verify" pass is not registered.
7 ; STOP-BEFORE-CTR-LOOPS-VERIFY-NOT: PowerPC CTR Loops Verify
9 …ter=ppc-ctr-loops-verify -o /dev/null 2>&1 | FileCheck %s -check-prefix=STOP-AFTER-CTR-LOOPS-VERIFY
10 ; STOP-AFTER-CTR-LOOPS-VERIFY: -ppc-ctr-loops-verify
11 ; STOP-AFTER-CTR-LOOPS-VERIFY-NOT: "ppc-ctr-loops-verify" pass is not registered.
12 ; STOP-AFTER-CTR-LOOPS-VERIFY: PowerPC CTR Loops Verify
H A Dctrloop-large-ec.ll19 ; On PPC32, CTR is also 32 bits, and so cannot hold a 64-bit count.
H A Dpr36292.ll6 ; No CTR loop due to frem (since it is always a call).
H A Dpr43527.ll4 ; We don't want to produce a CTR loop due to the call to lrint in the body.
H A DO3-pipeline.ll92 ; CHECK-NEXT: PowerPC CTR Loops Verify
134 ; CHECK-NEXT: PowerPC CTR loops generation
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCTRLoops.cpp117 return (MI->definesRegister(PPC::CTR) && in isCTRClobber()
118 !MI->registerDefIsDead(PPC::CTR)) || in isCTRClobber()
123 if ((MI->modifiesRegister(PPC::CTR) && !MI->registerDefIsDead(PPC::CTR)) || in isCTRClobber()
132 if (MI->readsRegister(PPC::CTR) || MI->readsRegister(PPC::CTR8)) in isCTRClobber()
180 if (Preheader->isLiveIn(PPC::CTR) || Preheader->isLiveIn(PPC::CTR8)) in processLoop()
H A DPPCCTRLoopsVerify.cpp86 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8)) in clobbersCTR()
89 if (MO.clobbersPhysReg(PPC::CTR) || MO.clobbersPhysReg(PPC::CTR8)) in clobbersCTR()
H A DPPCInstrInfo.td1253 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
1268 let Defs = [CTR], Uses = [CTR] in {
1364 let Defs = [CTR], Uses = [CTR, RM] in {
1390 let Defs = [CTR], Uses = [CTR, LR, RM] in {
2555 let hasSideEffects = 1, Uses = [CTR], Defs = [CTR] in
4644 let Defs = [CTR], Uses = [CTR, RM] in {
4662 let Defs = [LR, CTR], Uses = [CTR, RM] in {
4680 let Defs = [CTR], Uses = [CTR, LR, RM] in
4684 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in
4688 let Defs = [CTR], Uses = [CTR, LR, RM] in
[all …]
H A DPPCInstrInfo.cpp1412 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1498 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1515 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1543 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
2054 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in reverseBranchCondition()
2142 if (MI.definesRegister(PPC::CTR) || MI.definesRegister(PPC::CTR8)) in MBBDefinesCTR()
2188 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2211 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2250 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
2293 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
[all …]
H A DPPCRegisterInfo.td251 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
409 // The CTR registers are not allocatable because they're used by the
412 def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
H A DP9InstrResources.td934 (instregex "MF(SPR|CTR|LR)(8)?$"),
1307 (instregex "gBC(A|Aat|CTR|CTRL|L|LA|LAat|LR|LRL|Lat|at)?$"),
H A DPPCRegisterInfo.cpp353 markSuperRegs(Reserved, PPC::CTR); in getReservedRegs()
H A DPPCISelLowering.cpp5527 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT)); in buildCallOperands()
5596 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || in FinishCall()
/llvm-project-15.0.7/llvm/test/Transforms/StructurizeCFG/
H A Dloop-continue-phi.ll11 ; CHECK-NEXT: [[CTR:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[CTR_NEXT:%.*]], [[FLOW1]] ]
12 ; CHECK-NEXT: [[CTR_NEXT]] = add i32 [[CTR]], 1
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Core/
H A DSVals.cpp49 if (const FunctionCodeRegion *CTR = R->getAs<FunctionCodeRegion>()) in getAsFunctionDecl() local
50 if (const auto *FD = dyn_cast<FunctionDecl>(CTR->getDecl())) in getAsFunctionDecl()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZ196.td605 (instregex "KM(C|F|O|CTR)?$")>;
1221 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1224 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1225 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
H A DSystemZScheduleZEC12.td618 (instregex "KM(C|F|O|CTR)?$")>;
1266 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1269 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1270 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
H A DSystemZScheduleZ13.td647 (instregex "KM(C|F|O|CTR)?$")>;
1540 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1543 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1544 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
H A DSystemZScheduleZ16.td671 (instregex "KM(C|F|O|CTR|A)?$")>;
1709 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1712 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1713 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
H A DSystemZScheduleZ15.td671 (instregex "KM(C|F|O|CTR|A)?$")>;
1676 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1679 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1680 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
H A DSystemZScheduleZ14.td657 (instregex "KM(C|F|O|CTR|A)?$")>;
1630 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
1633 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
1634 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
/llvm-project-15.0.7/llvm/docs/
H A DReleaseNotes.rst176 * Add a new post instruction selection pass to generate CTR loops.
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1201 RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR; in MatchRegisterName()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dwqm.ll1822 ; CHECK-DAG: v_mov_b32_e32 [[CTR:v[0-9]+]], 0
1826 ; CHECK: v_add_f32_e32 [[CTR]], 2.0, [[CTR]]
1828 ; CHECK: v_cmp_lt_f32_e32 vcc, [[SEVEN]], [[CTR]]