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/llvm-project-15.0.7/mlir/test/Integration/Dialect/SparseTensor/CPU/
H A Dsparse_matmul.mlir6 #CSR = #sparse_tensor.encoding<{
32 %B: tensor<8x4xf64, #CSR>) -> tensor<4x4xf64, #CSR> {
35 ins(%A, %B: tensor<4x8xf64, #CSR>, tensor<8x4xf64, #CSR>)
36 outs(%C: tensor<4x4xf64, #CSR>) -> tensor<4x4xf64, #CSR>
37 return %D: tensor<4x4xf64, #CSR>
109 : (tensor<4x8xf64, #CSR>,
110 tensor<8x4xf64, #CSR>) -> tensor<4x4xf64, #CSR>
119 : (tensor<4x8xf64, #CSR>,
120 tensor<8x4xf64, #CSR>) -> tensor<4x4xf64, #CSR>
129 : (tensor<4x8xf64, #CSR>,
[all …]
H A Dsparse_scale.mlir15 #CSR = #sparse_tensor.encoding<{ dimLevelType = [ "dense", "compressed" ] }>
34 func.func @sparse_scale(%argx: tensor<8x8xf32, #CSR>) -> tensor<8x8xf32, #CSR> {
37 outs(%argx: tensor<8x8xf32, #CSR>) {
41 } -> tensor<8x8xf32, #CSR>
42 return %0 : tensor<8x8xf32, #CSR>
67 %1 = sparse_tensor.convert %0 : tensor<8x8xf32> to tensor<8x8xf32, #CSR>
69 : (tensor<8x8xf32, #CSR>) -> tensor<8x8xf32, #CSR>
75 %m = sparse_tensor.values %2 : tensor<8x8xf32, #CSR> to memref<?xf32>
80 bufferization.dealloc_tensor %1 : tensor<8x8xf32, #CSR>
H A Dsparse_storage.mlir15 #CSR = #sparse_tensor.encoding<{
77 %1 = sparse_tensor.convert %t : tensor<10x8xf64> to tensor<10x8xf64, #CSR>
98 // Inspect storage scheme of CSR.
108 %7 = sparse_tensor.pointers %1, %c1 : tensor<10x8xf64, #CSR> to memref<?xindex>
111 %9 = sparse_tensor.indices %1, %c1 : tensor<10x8xf64, #CSR> to memref<?xindex>
114 %11 = sparse_tensor.values %1 : tensor<10x8xf64, #CSR> to memref<?xf64>
250 bufferization.dealloc_tensor %1 : tensor<10x8xf64, #CSR>
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonGenExtract.cpp100 ConstantInt *CSL = nullptr, *CSR = nullptr, *CM = nullptr; in INITIALIZE_PASS_DEPENDENCY() local
107 bool Match = match(In, m_And(m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
114 Match = match(In, m_And(m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
121 CSR = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in INITIALIZE_PASS_DEPENDENCY()
131 Match = match(In, m_And(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
138 Match = match(In, m_And(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
145 Match = match(In, m_Shl(m_LShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
152 Match = match(In, m_Shl(m_AShr(m_Value(BF), m_ConstantInt(CSR)), in INITIALIZE_PASS_DEPENDENCY()
165 uint32_t SR = CSR->getZExtValue(); in INITIALIZE_PASS_DEPENDENCY()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DShrinkWrapping.cpp893 if (!CSA.CalleeSaved[CSR]) in isBestSavePosCold()
896 assert(BestSaveCount[CSR].size() == BestSavePos[CSR].size() && in isBestSavePosCold()
1063 dbgs() << "Reg " << CSR in validatePushPopsMode()
1071 dbgs() << "Reg " << CSR in validatePushPopsMode()
1097 dbgs() << "Reg " << CSR in validatePushPopsMode()
1108 unsigned CSR) { in fixPopsPlacements() argument
1119 BV &= UsesByReg[CSR]; in fixPopsPlacements()
1169 if (SavedReg != CSR && RestoredReg != CSR) { in scheduleOldSaveRestoresRemoval()
1181 SavedReg == CSR && DeletedPushCFIs[CSR].empty(); in scheduleOldSaveRestoresRemoval()
1183 RestoredReg == CSR && DeletedPopCFIs[CSR].empty(); in scheduleOldSaveRestoresRemoval()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dspill-stack-realignment.mir3 # Ensure references to scavenged stack slots in the CSR area use the
6 # alignment padding area is between the CSR area and the SP, so the SP
7 # cannot be used to reference the CSR area.
33 ; Force preserve a CSR to create a hole in the CSR stack region.
H A Dstack-id-stackslot-scavenging.mir5 # creates a hole in the CSR stack region, but it should not be saved to.
21 ; Force preserve a CSR to create a hole in the CSR stack region.
H A Dframelayout-fp-csr.ll6 ; record, which is located 16 bytes above the end of the CSR
7 ; space when a single FP CSR is in use.
H A Dreverse-csr-restore-seq.mir61 ; The local stack size is not 0, and we can combine the CSR stack size with
64 ; In this case, there is no point of moving the first CSR pair at the end.
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveRegUnits.cpp85 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) { in addCalleeSavedRegs() local
86 const unsigned N = *CSR; in addCalleeSavedRegs()
H A DRegisterClassInfo.cpp59 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); in runOnMachineFunction() local
60 if (Update || CSR != CalleeSavedRegs) { in runOnMachineFunction()
64 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
70 CalleeSavedRegs = CSR; in runOnMachineFunction()
75 for (const MCPhysReg *I = CSR; *I; ++I) in runOnMachineFunction()
H A DMachineFrameInfo.cpp125 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; in getPristineRegs() local
126 ++CSR) in getPristineRegs()
127 BV.set(*CSR); in getPristineRegs()
H A DLivePhysRegs.cpp177 for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR) in addCalleeSavedRegs() local
178 LiveRegs.addReg(*CSR); in addCalleeSavedRegs()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86MachineFunctionInfo.cpp30 for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); in setRestoreBasePointer() local
31 unsigned Reg = *CSR; ++CSR) { in setRestoreBasePointer()
/llvm-project-15.0.7/bolt/include/bolt/Passes/
H A DShrinkWrapping.h375 bool validateBestSavePos(unsigned CSR, MCInst *&BestPosSave,
403 bool isBestSavePosCold(unsigned CSR, MCInst *&BestPosSave,
420 unsigned CSR,
425 bool validatePushPopsMode(unsigned CSR, MCInst *BestPosSave,
432 int64_t SaveOffset, unsigned CSR);
435 void scheduleOldSaveRestoresRemoval(unsigned CSR, bool UsePushPops);
437 bool doesInstUsesCSR(const MCInst &Inst, uint16_t CSR);
440 scheduleSaveRestoreInsertions(unsigned CSR, MCInst *BestPosSave,
456 void insertUpdatedCFI(unsigned CSR, int SPValPush, int SPValPop);
H A DLivenessAnalysis.h116 BitVector CSR = BitVector(NumRegs, false); in computeNext() local
117 BC.MIB->getCalleeSavedRegs(CSR); in computeNext()
118 CSR.flip(); in computeNext()
119 Written |= CSR; in computeNext()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcfi-inserter-verify-inconsistent-loc.mir4 # Test that CSR being saved in multiple locations can be caught by
13 # CHECK: Different saved locations for the same CSR
H A Dcfi-inserter-verify-inconsistent-csr.mir16 # CHECK: *** Inconsistent CSR Saved between pred and succ in function inconsistentCSR ***
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SparseTensor/IR/
H A DSparseTensorOps.td45 sparse_tensor.new %source : !Source to tensor<1024x1024xf64, #CSR>
110 : tensor<64x64xf64, #CSR> to memref<?xindex>
135 : tensor<64x64xf64, #CSR> to memref<?xindex>
195 : tensor<1024x1024xf64, #CSR>, memref<?xindex>, memref<f64>
267 : tensor<4x4xf64, #CSR>, memref<?xindex>, memref<?xf64>,
391 ins(%A: tensor<?x?xf64, #CSR>, %B: tensor<?x?xf64, #CSR>
392 outs(%C: tensor<?x?xf64, #CSR> {
414 } -> tensor<?x?xf64, #CSR>
424 ins(%A: tensor<?x?xf64, #CSR>, %B: tensor<?x?xi32, #CSR>
425 outs(%C: tensor<?x?xf64, #CSR> {
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SparseTensor/
H A Droundtrip_encoding.mlir9 #CSR = #sparse_tensor.encoding<{
18 func.func private @sparse_2d_tensor(tensor<?x?xf32, #CSR>)
H A Dsparse_parallel.mlir20 #CSR = #sparse_tensor.encoding<{
156 func.func @matvec(%arga: tensor<16x32xf32, #CSR>,
160 ins(%arga, %argb : tensor<16x32xf32, #CSR>, tensor<32xf32>)
/llvm-project-15.0.7/llvm/test/DebugInfo/X86/
H A Dspill-nospill.ll5 ; each. x must be spilled, but y will be allocated to a CSR. x's location
31 ; CHECK: movl %eax, %[[CSR:[^ ]*]]
35 ; CHECK: movl %[[CSR]], %ecx
37 ; CHECK: movl %[[CSR]], %ecx
41 ; CHECK: addl %[[CSR]], %eax
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmir-print-dead-csr-fi.mir4 # CSR SGPR frame indexes are inserted, but deleted.
H A Dcallee-frame-setup.ll129 ; spilling CSR SGPRs.
164 ; Make sure if a CSR vgpr is used for SGPR spilling, it is saved and
208 ; Has no spilled CSR VGPRs used for SGPR spilling, so no need to
265 ; Use a copy to a free SGPR instead of introducing a second CSR VGPR.
311 ; Use a copy to a free SGPR instead of introducing a second CSR VGPR.
428 ; Need a new CSR VGPR to satisfy the FP spill.
474 ; register is needed to access the CSR VGPR slot.
513 ; Use all clobberable VGPRs, so a CSR spill is needed for the VGPR
608 call void asm sideeffect "; clobber all VGPRs except CSR v40",
643 call void asm sideeffect "; clobber all VGPRs except CSR v40",
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td278 // R8 is used to pass swifterror, remove it from CSR.
281 // R10 is used to pass swiftself, remove it from CSR.
296 // R8 is used to pass swifterror, remove it from CSR.
300 // R10 is used to pass swifterror, remove it from CSR.
325 // R8 is used to pass swifterror, remove it from CSR.
328 // R10 is used to pass swiftself, remove it from CSR.

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