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Searched refs:CSNEG (Results 1 – 15 of 15) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-select.mir353 ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc
383 ; G_SELECT cc, (G_SUB 0, %x), %false -> CSNEG %x, %false, inv_cc
413 ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h321 CSNEG, // Conditional select negate. enumerator
H A DARMISelLowering.cpp1869 MAKE_CASE(ARMISD::CSNEG) in getTargetNodeName()
5417 Opcode = ARMISD::CSNEG; in LowerSELECT_CC()
18650 case ARMISD::CSNEG: in PerformDAGCombine()
19871 case ARMISD::CSNEG: { in computeKnownBitsForTargetNode()
19884 else if (Op.getOpcode() == ARMISD::CSNEG) in computeKnownBitsForTargetNode()
H A DARMInstrInfo.td119 def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel, [SDNPOptInGlue]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td436 "CSNEG(W|X)r")>;
458 "CSNEG(W|X)r")>;
477 "CSNEG(W|X)r")>;
H A DAArch64SchedThunderX3T110.td695 "CSNEG(W|X)r")>;
717 "CSNEG(W|X)r")>;
736 "CSNEG(W|X)r")>;
H A DAArch64ISelLowering.h72 CSNEG, // Conditional select negate. enumerator
H A DAArch64SchedCyclone.td149 // CSEL,CSINC,CSINV,CSNEG
H A DAArch64SchedTSV110.td380 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedAmpere1.td948 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
H A DAArch64SchedA64FX.td830 "CSNEG(W|X)r")>;
851 "CSNEG(W|X)r")>;
869 "CSNEG(W|X)r")>;
H A DAArch64ISelLowering.cpp2055 MAKE_CASE(AArch64ISD::CSNEG) in getTargetNodeName()
8168 Opcode = AArch64ISD::CSNEG; in LowerSELECT_CC()
8223 } else if (Opcode == AArch64ISD::CSNEG && RHSVal && RHSVal->isOne()) { in LowerSELECT_CC()
14060 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, And, And, CCVal, Cmp); in BuildSREMPow2()
14071 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, AndPos, AndNeg, CCVal, in BuildSREMPow2()
15709 LHS.getOpcode() != AArch64ISD::CSNEG) { in performAddCSelIntoCSinc()
15712 LHS.getOpcode() != AArch64ISD::CSNEG) { in performAddCSelIntoCSinc()
15732 !(LHS.getOpcode() == AArch64ISD::CSNEG && in performAddCSelIntoCSinc()
15745 if (LHS.getOpcode() == AArch64ISD::CSNEG && CTVal->isOne() && in performAddCSelIntoCSinc()
15761 (LHS.getOpcode() == AArch64ISD::CSNEG && CFVal->isAllOnes())) && in performAddCSelIntoCSinc()
H A DAArch64SchedFalkorDetails.td894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedKryoDetails.td549 (instregex "(CSINC|CSNEG)(W|X)r")>;
H A DAArch64InstrInfo.td552 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
2310 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;