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Searched refs:CSINC (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-select.mir98 ; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
154 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
212 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
241 ; G_SELECT cc, t, -1 -> CSINC t, zreg, cc
270 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
297 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc
324 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
603 ; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc
632 ; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc
661 ; G_SELECT cc, %true, (G_PTR_ADD %x, 1) -> CSINC %true, %x, cc
H A Dselect-cmp.mir294 ; The CSINC should use the add's RHS.
325 ; The CSINC should use the add's LHS.
356 ; We don't emit CSINC with vectors, so there should be no optimization here.
387 ; The CSINC should use the add's RHS.
H A Dfold-brcond-fcmp.mir4 # Test that we don't have to emit a CSINC when emitting a G_FCMP being used by
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dcond-sel-value-prop.ll59 ; CSINC to materialize the 1.
H A Darm64-early-ifcvt.ll396 ; This function from 175.vpr folds an ADDWri into a CSINC.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h322 CSINC, // Conditional select increment. enumerator
H A DARMISelLowering.cpp1870 MAKE_CASE(ARMISD::CSINC) in getTargetNodeName()
5419 Opcode = ARMISD::CSINC; in LowerSELECT_CC()
5421 Opcode = ARMISD::CSINC; in LowerSELECT_CC()
5430 if (Opcode != ARMISD::CSINC && in LowerSELECT_CC()
13814 SDValue CSINC = N->getOperand(1); in PerformSubCSINCCombine() local
13815 if (CSINC.getOpcode() != ARMISD::CSINC || !CSINC.hasOneUse()) in PerformSubCSINCCombine()
13825 CSINC.getOperand(1), CSINC.getOperand(2), in PerformSubCSINCCombine()
13826 CSINC.getOperand(3)); in PerformSubCSINCCombine()
18648 case ARMISD::CSINC: in PerformDAGCombine()
19869 case ARMISD::CSINC: in computeKnownBitsForTargetNode()
[all …]
H A DARMInstrInfo.td120 def ARMcsinc : SDNode<"ARMISD::CSINC", SDT_ARMCSel, [SDNPOptInGlue]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td435 "CSINC(W|X)r", "CSINV(W|X)r",
457 "CSINC(W|X)r", "CSINV(W|X)r",
476 "CSINC(W|X)r", "CSINV(W|X)r",
H A DAArch64SchedThunderX3T110.td694 "CSINC(W|X)r", "CSINV(W|X)r",
716 "CSINC(W|X)r", "CSINV(W|X)r",
735 "CSINC(W|X)r", "CSINV(W|X)r",
H A DAArch64ISelLowering.h73 CSINC, // Conditional select increment. enumerator
H A DAArch64SchedCyclone.td149 // CSEL,CSINC,CSINV,CSNEG
H A DAArch64SchedTSV110.td380 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedAmpere1.td948 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
H A DAArch64SchedA64FX.td829 "CSINC(W|X)r", "CSINV(W|X)r",
850 "CSINC(W|X)r", "CSINV(W|X)r",
868 "CSINC(W|X)r", "CSINV(W|X)r",
H A DAArch64SchedFalkorDetails.td894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedKryoDetails.td549 (instregex "(CSINC|CSNEG)(W|X)r")>;
H A DAArch64ISelLowering.cpp2056 MAKE_CASE(AArch64ISD::CSINC) in getTargetNodeName()
8179 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
8187 Opcode = AArch64ISD::CSINC; in LowerSELECT_CC()
15768 return DAG.getNode(AArch64ISD::CSINC, DL, VT, NewNode, RHS, CCVal, Cmp); in performAddCSelIntoCSinc()
15952 return DAG.getNode(AArch64ISD::CSINC, DL, VT, LHS, LHS, CC, Cond); in foldADCToCINC()
19860 AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32), in PerformDAGCombine()
H A DAArch64InstrInfo.td553 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
2308 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp4724 auto CSINC = MIRBuilder.buildInstr(Opc, {Dst}, {Src1, Src2}).addImm(Pred); in emitCSINC() local
4725 constrainSelectedInstRegOperands(*CSINC, TII, TRI, RBI); in emitCSINC()
4726 return &*CSINC; in emitCSINC()