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Searched refs:CSEL (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-arithmetic-encoding.s569 CSEL W16, W7, W27, EQ
570 CSEL W15, W6, W26, NE
571 CSEL W14, W5, W25, CS
572 CSEL W13, W4, W24, HS
578 CSEL X7, X7, X3, VC
579 CSEL X6, X7, X4, HI
580 CSEL X5, X6, X5, LS
581 CSEL X4, X5, X6, GE
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfcsel-zero.ll1 ; Check that 0.0 is not materialized for CSEL when comparing against it.
H A Dearly-ifcvt-regclass-mismatch.mir115 ; Here we check that we don't ifcvt to a CSEL that uses GPRs, because
H A Dfold-csel-cttz-and.ll5 ;; CSEL 0, cttz, cc -> AND cttz numbits-1
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1890 case AArch64ISD::CSEL: { in computeKnownBitsForTargetNode()
2053 MAKE_CASE(AArch64ISD::CSEL) in getTargetNodeName()
8128 unsigned Opcode = AArch64ISD::CSEL; in LowerSELECT_CC()
8201 if (Opcode != AArch64ISD::CSEL) { in LowerSELECT_CC()
14764 CSel1.getOpcode() != AArch64ISD::CSEL) in performANDORCSELCombine()
15570 if (Op.getOpcode() != AArch64ISD::CSEL) in isSetCC()
15708 if (LHS.getOpcode() != AArch64ISD::CSEL && in performAddCSelIntoCSinc()
15898 if (Op.getOpcode() != AArch64ISD::CSEL) in getCSETCondCode()
18377 SDValue CSEL = in performSETCCCombine() local
18381 return DAG.getZExtOrTrunc(CSEL, DL, VT); in performSETCCCombine()
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H A DAArch64SchedThunderX2T99.td434 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
456 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
475 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
H A DAArch64SchedThunderX3T110.td693 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
715 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
734 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
H A DAArch64ISelLowering.h70 CSEL, enumerator
H A DAArch64SchedCyclone.td149 // CSEL,CSINC,CSINV,CSNEG
H A DAArch64SchedTSV110.td380 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedAmpere1.td948 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
H A DAArch64SchedA64FX.td828 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
849 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
867 "CCMP(W|X)(i|r)", "CSEL(W|X)r",
H A DAArch64SchedFalkorDetails.td894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedKryoDetails.td543 (instregex "CSEL(W|X)r")>;
H A DAArch64InstrInfo.td550 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
2305 defm CSEL : CondSelect<0, 0b00, "csel">;
4208 // CSEL instructions providing f128 types need to be handled by a
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td426 // CSEL aliases inverted predicate
758 // CSEL). Setting Unpredictable{15} = 1 here would reintroduce