1890   case AArch64ISD::CSEL: {  in computeKnownBitsForTargetNode()
2053     MAKE_CASE(AArch64ISD::CSEL)  in getTargetNodeName()
3506     return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,  in LowerXOR()
3556     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,  in LowerXOR()
3586   return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Flag);  in carryFlagToValue()
3596   return DAG.getNode(AArch64ISD::CSEL, DL, VT, One, Zero, CC, Flag);  in overflowFlagToValue()
3646   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,  in LowerXALUO()
5332   return DAG.getNode(AArch64ISD::CSEL, DL, VT, Op.getOperand(0), Neg,  in LowerABS()
8039     SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
8066     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);  in LowerSETCC()
8076         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSETCC()
8079     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSETCC()
8128     unsigned Opcode = AArch64ISD::CSEL;  in LowerSELECT_CC()
8201       if (Opcode != AArch64ISD::CSEL) {  in LowerSELECT_CC()
8214     if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&  in LowerSELECT_CC()
8273   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSELECT_CC()
8279     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSELECT_CC()
8375     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,  in LowerSELECT()
14009   SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);  in BuildSDIVPow2()
14763   if (CSel0.getOpcode() != AArch64ISD::CSEL ||  in performANDORCSELCombine()
14764       CSel1.getOpcode() != AArch64ISD::CSEL)  in performANDORCSELCombine()
14810   return DAG.getNode(AArch64ISD::CSEL, DL, VT, CSel0.getOperand(0),  in performANDORCSELCombine()
15570   if (Op.getOpcode() != AArch64ISD::CSEL)  in isSetCC()
15656   return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);  in performSetccAddFolding()
15708   if (LHS.getOpcode() != AArch64ISD::CSEL &&  in performAddCSelIntoCSinc()
15711     if (LHS.getOpcode() != AArch64ISD::CSEL &&  in performAddCSelIntoCSinc()
15730   if (!(LHS.getOpcode() == AArch64ISD::CSEL &&  in performAddCSelIntoCSinc()
15737   if (LHS.getOpcode() == AArch64ISD::CSEL && CTVal->isOne() &&  in performAddCSelIntoCSinc()
15760   assert(((LHS.getOpcode() == AArch64ISD::CSEL && CFVal->isOne()) ||  in performAddCSelIntoCSinc()
15817   if (CSel.getOpcode() != AArch64ISD::CSEL || !CSel->hasOneUse())  in performNegCSelCombine()
15833   return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0N, N1N, CSel.getOperand(2),  in performNegCSelCombine()
15898   if (Op.getOpcode() != AArch64ISD::CSEL)  in getCSETCondCode()
16336   SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);  in getPTest()
18368       LHS->getOpcode() == AArch64ISD::CSEL &&  in performSETCCCombine()
18377     SDValue CSEL =  in performSETCCCombine()  local
18378         DAG.getNode(AArch64ISD::CSEL, DL, LHS.getValueType(), LHS.getOperand(0),  in performSETCCCombine()
18381     return DAG.getZExtOrTrunc(CSEL, DL, VT);  in performSETCCCombine()
19578   case AArch64ISD::CSEL:  in PerformDAGCombine()