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Searched refs:CS1 (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dwineh-unreachable.ll29 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch.body] unwind to caller
31 ; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS1]] []
93 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch.body] unwind to caller
95 ; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS1]] []
121 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch.body] unwind to caller
123 ; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS1]] [i8* null, i32 0, i8* null]
149 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch.body] unwind to caller
151 ; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS1]] [i8* null, i32 0, i8* null]
183 ; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS1]] [i8* null, i32 0, i8* null]
215 ; CHECK-NEXT: [[CATCH:%.*]] = catchpad within [[CS1]] [i8* null, i32 0, i8* null]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IROutliner/
H A Dillegal-catchpad.ll18 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catchpad1] unwind to caller
20 ; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS1]] []
49 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catchpad1] unwind to caller
51 ; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS1]] []
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A DProfileSummaryInfoTest.cpp149 CallBase &CS1 = cast<CallBase>(*BB1->getFirstNonPHI()); in TEST_F() local
150 EXPECT_FALSE(PSI.isHotCallSite(CS1, &BFI)); in TEST_F()
151 EXPECT_FALSE(PSI.isColdCallSite(CS1, &BFI)); in TEST_F()
243 CallBase &CS1 = cast<CallBase>(*BB1->getFirstNonPHI()); in TEST_F() local
247 EXPECT_TRUE(PSI.isHotCallSite(CS1, &BFI)); in TEST_F()
339 CallBase &CS1 = cast<CallBase>(*BB1->getFirstNonPHI()); in TEST_F() local
348 EXPECT_FALSE(PSI.isHotCallSite(CS1, &BFI)); in TEST_F()
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/X86/
H A Dempty-cleanuppad.ll69 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch] unwind to caller
71 ; CHECK-NEXT: [[TMP1:%.*]] = catchpad within [[CS1]] [i8* null, i32 64, i8* null]
131 ; CHECK-NEXT: [[CP2:%.*]] = catchpad within [[CS1]] [i8* null, i32 64, i8* null]
196 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch] unwind to caller
198 ; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS1]] [i8* null, i32 64, i8* null]
255 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch] unwind to caller
257 ; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS1]] [i8* null, i32 64, i8* null]
322 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch] unwind to caller
324 ; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS1]] [i8* null, i32 64, i8* null]
399 ; CHECK-NEXT: [[TMP0:%.*]] = catchpad within [[CS1]] [i8* null, i32 64, i8* null]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/
H A Dmultiblock-exceptions.ll23 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch] unwind label [[CLEANUP:%.*]]
25 ; CHECK-NEXT: [[C:%.*]] = catchpad within [[CS1]] []
/llvm-project-15.0.7/llvm/test/ExecutionEngine/MCJIT/
H A Dtest-common-symbols-alignment.ll7 @CS1 = common global i32 0, align 16
/llvm-project-15.0.7/clang/test/Index/
H A Dprint-type-size.cpp374 struct CS1 { in f() struct
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/X86/
H A Dlivedebugvalues-limit.mir20 …![[INLCS1:[0-9]+]] = !DILocation(line: 3, column: 41, scope: ![[F_SP]], inlinedAt: ![[CS1:[0-9]+]])
21 ; CHECK: ![[CS1]] = distinct !DILocation(line: 5, column: 3, scope: !{{[0-9]+}})
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dv7k-abi-align.ll78 ; If there's only a CS1 area, the sub should be in the right place:
/llvm-project-15.0.7/llvm/docs/
H A DAliasAnalysis.rst151 dependencies between function calls. This method takes two call sites (``CS1``
153 written by the other, ``Ref`` if ``CS1`` reads memory written by ``CS2``,
154 ``Mod`` if ``CS1`` writes to memory read or written by ``CS2``, or ``ModRef`` if
155 ``CS1`` might read or write memory written to by ``CS2``. Note that this
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp172 Reserved.set(Hexagon::CS1); // C13 in getReservedRegs()
H A DHexagonRegisterInfo.td194 def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>;
213 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>;
560 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
H A DHexagonInstrInfo.cpp1055 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
H A DHexagonISelLowering.cpp336 .Case("cs1", Hexagon::CS1) in getRegisterByName()
/llvm-project-15.0.7/llvm/test/Transforms/GVN/PRE/
H A Dpre-load.ll563 ; CHECK-NEXT: [[CS1:%.*]] = catchswitch within none [label %catch] unwind label [[CLEANUP2:%.*]]
565 ; CHECK-NEXT: [[C:%.*]] = catchpad within [[CS1]] []
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp676 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, in DecodeCtrRegsRegisterClass()
/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DAttributorAttributes.cpp191 ChangeStatus CS1 = clampStateAndIndicateChange(S.GlobalState, R.GlobalState); in PIPE_OPERATOR() local
192 return CS0 | CS1; in PIPE_OPERATOR()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp8075 SDValue CS1 = in LowerSETCC() local
8079 Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSETCC()
8273 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); in LowerSELECT_CC() local
8279 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSELECT_CC()
8283 return CS1; in LowerSELECT_CC()