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Searched refs:CPol (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp278 AMDGPU::CPol::CPol Bit) const;
481 return enableNamedBit(MI, AMDGPU::CPol::NT); in enableNTBit()
831 AMDGPU::CPol::CPol Bit) const { in enableNamedBit()
833 if (!CPol) in enableNamedBit()
836 CPol->setImm(CPol->getImm() | Bit); in enableNamedBit()
1434 .addImm(AMDGPU::CPol::SC0 | AMDGPU::CPol::SC1); in insertRelease()
1636 .addImm(AMDGPU::CPol::SC0 | AMDGPU::CPol::SC1); in insertAcquire()
1650 .addImm(AMDGPU::CPol::SC1); in insertAcquire()
1668 .addImm(AMDGPU::CPol::SC0); in insertAcquire()
1723 .addImm(AMDGPU::CPol::SC0 | AMDGPU::CPol::SC1); in insertRelease()
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H A DMIMGInstructions.td373 Dim:$dim, UNorm:$unorm, CPol:$cpol,
386 Dim:$dim, UNorm:$unorm, CPol:$cpol,
398 Dim:$dim, UNorm:$unorm, CPol:$cpol,
411 Dim:$dim, UNorm:$unorm, CPol:$cpol,
556 Dim:$dim, UNorm:$unorm, CPol:$cpol,
582 Dim:$dim, UNorm:$unorm, CPol:$cpol,
678 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
691 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
742 Dim:$dim, UNorm:$unorm, CPol:$cpol,
772 Dim:$dim, UNorm:$unorm, CPol:$cpol,
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H A DSMInstructions.td125 !con((ins baseClass:$sbase), offsets.Ins, (ins CPol:$cpol)),
176 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, CPol:$cpol),
183 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soffset, CPol:$cpol),
191 CPol:$cpol),
279 Operand CPolTy = !if(isRet, CPol_GLC1, CPol)> :
506 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$soffset, CPol:$cpol);
577 let InOperandList = !con((ins BaseClass:$sbase), offsets.Ins, (ins CPol:$cpol));
613 offsets, (ins CPol:$cpol));
1008 let InOperandList = !con((ins BaseClass:$sbase), offsets.Ins, (ins CPol:$cpol));
1037 SReg_32:$soffset, smem_offset_mod:$offset, CPol:$cpol);
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H A DSILoadStoreOptimizer.cpp115 unsigned CPol = 0; member
688 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
914 CI.CPol == Paired.CPol; in offsetsCanBeCombined()
1317 .addImm(CI.CPol) // cpol in mergeSBufferLoadImmPair()
1371 .addImm(CI.CPol) // cpol in mergeBufferLoadPair()
1431 .addImm(CI.CPol) // cpol in mergeTBufferLoadPair()
1503 .addImm(CI.CPol) // cpol in mergeTBufferStorePair()
1532 .addImm(CI.CPol) in mergeFlatLoadPair()
1590 .addImm(CI.CPol) in mergeFlatStorePair()
1798 .addImm(CI.CPol) // cpol in mergeBufferStorePair()
H A DSIDefines.h301 namespace CPol {
303 enum CPol { enum
H A DAMDGPUInstructionSelector.cpp1640 unsigned CPol = MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(); in selectImageIntrinsic() local
1642 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in selectImageIntrinsic()
1643 if (CPol & ~AMDGPU::CPol::ALL) in selectImageIntrinsic()
1749 MIB.addImm(CPol); in selectImageIntrinsic()
3212 MIB.addImm(Aux & AMDGPU::CPol::ALL); // cpol in selectBufferLoadLds()
4843 MIB.addImm(AMDGPU::CPol::GLC); // cpol in selectMUBUFAddr64Atomic()
4868 [=](MachineInstrBuilder &MIB) { MIB.addImm(AMDGPU::CPol::GLC); } // cpol in selectMUBUFOffsetAtomic()
4962 MIB.addImm(MI.getOperand(OpIdx).getImm() & AMDGPU::CPol::ALL); in renderExtractCPol()
4976 MIB.addImm(MI.getOperand(OpIdx).getImm() | AMDGPU::CPol::GLC); in renderSetGLC()
H A DSIInstrInfo.td923 return CurDAG->getTargetConstant(N->getZExtValue() & AMDGPU::CPol::ALL, SDLoc(N), MVT::i8);
931 return CurDAG->getTargetConstant(N->getZExtValue() | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8);
1237 def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>;
1238 def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>;
1239 def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>;
H A DFLATInstructions.td168 !if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
282 (ins flat_offset:$offset, CPol:$cpol)),
323 !if(HasTiedOutput, (ins CPol:$cpol, getLdStRegisterOperand<regClass>.ret:$vdst_in),
406 (ins VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
408 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
410 (ins VGPR_32:$vaddr, flat_offset:$offset, CPol:$cpol),
411 (ins flat_offset:$offset, CPol:$cpol)))),
H A DBUFInstructions.td145 offset:$offset, FORMAT:$format, CPol:$cpol, TFE:$tfe, SWZ:$swz),
147 offset:$offset, FORMAT:$format, CPol:$cpol, TFE:$tfe, SWZ:$swz)
151 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol,
154 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol,
631 (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, SWZ:$swz),
H A DSIISelLowering.cpp6579 unsigned CPol = cast<ConstantSDNode>( in lowerImage() local
6582 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in lowerImage()
6583 if (CPol & ~AMDGPU::CPol::ALL) in lowerImage()
6600 Ops.push_back(DAG.getTargetConstant(CPol, DL, MVT::i32)); in lowerImage()
6938 unsigned CPol = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); in LowerINTRINSIC_WO_CHAIN() local
6939 if (CPol & ~AMDGPU::CPol::ALL) in LowerINTRINSIC_WO_CHAIN()
8278 DAG.getTargetConstant(Aux & AMDGPU::CPol::ALL, DL, MVT::i8)); // cpol in LowerINTRINSIC_VOID()
H A DSIInstrInfo.cpp5992 if (const MachineOperand *CPol = in legalizeOperands() local
5994 MIB.addImm(CPol->getImm()); in legalizeOperands()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4452 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
4458 if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) { in validateCoherencyBits()
4470 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
4476 if (CPol & CPol::GLC) { in validateCoherencyBits()
5927 CPolOn = AMDGPU::CPol::NT; in parseCPol()
5938 CPolOn = AMDGPU::CPol::GLC; in parseCPol()
5940 CPolOff = AMDGPU::CPol::GLC; in parseCPol()
5942 CPolOn = AMDGPU::CPol::SLC; in parseCPol()
5944 CPolOff = AMDGPU::CPol::SLC; in parseCPol()
5946 CPolOn = AMDGPU::CPol::DLC; in parseCPol()
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp207 if (Imm & CPol::GLC) in printCPol()
211 if (Imm & CPol::SLC) in printCPol()
213 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
215 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
217 if (Imm & ~CPol::ALL) in printCPol()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp612 unsigned CPol = in getInstruction() local
614 AMDGPU::CPol::GLC : 0; in getInstruction()
616 insertNamedMCOperand(MI, MCOperand::createImm(CPol), in getInstruction()
618 } else if (CPol) { in getInstruction()
619 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); in getInstruction()