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Searched refs:CMPri (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dexpand-pseudos.mir32 ; CHECK: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
37 CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
56 ; CHECK: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
62 CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr
81 ; CHECK: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr
84 CMPri $r1, 500, 14, $noreg, implicit-def $cpsr
H A Dmachine-outliner-unsafe-registers.mir27 CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
36 CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
72 CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
91 CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
99 CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
107 CMPri $r12, 42, 14, $noreg, implicit-def $cpsr
H A Dmachine-sink-multidef.mir53 ; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
62 ; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
73 CMPri %7, 0, 14, $noreg, implicit-def $cpsr
83 CMPri %7, 0, 14, $noreg, implicit-def $cpsr
H A Dcmpxchg.mir28 ; CHECK-NEXT: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
58 ; CHECK-NEXT: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
H A Difcvt-size.mir263 # CHECK: CMPri
279 CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
412 # CHECK: CMPri
420 CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
H A Dcortex-a57-misched-alu.ll42 ; CHECK-SAME: CMPri
H A Dno-register-coalescing-in-returnsTwice.mir112 CMPri killed %7, 0, 14, $noreg, implicit-def $cpsr
161 CMPri killed %15, 0, 14, $noreg, implicit-def $cpsr
H A Ddbg-range-extension.mir230 CMPri $r4, 0, 14, $noreg, implicit-def $cpsr, debug-location !25
/llvm-project-15.0.7/llvm/test/DebugInfo/ARM/
H A Dline.test5 ; branch, then further lowered to CMPri + brcc but without the fidelity that
H A Dmachine-cp-updates-dbg-reg.mir169 CMPri renamable $r4, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
177 CMPri renamable $r4, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/ARM/
H A Dif-coverter-call-site-info.mir144 CMPri renamable $r0, 0, 14, $noreg, implicit-def $cpsr, debug-location !22
151 CMPri renamable $r1, 0, 14, $noreg, implicit-def $cpsr, debug-location !22
H A Dlive-debug-values-reg-copy.mir124 CMPri renamable $r0, 10, 14, $noreg, implicit-def $cpsr, debug-location !16
H A Ddbgcall-site-propagated-value.mir163 CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr, debug-location !38
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp133 case ARM::CMPri: in LowerARMMachineInstrToMCInst()
H A DARMExpandPseudoInsts.cpp1798 unsigned CMPri = in ExpandCMP_SWAP() local
1799 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri; in ExpandCMP_SWAP()
1800 BuildMI(StoreBB, DL, TII->get(CMPri)) in ExpandCMP_SWAP()
1920 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64() local
1921 BuildMI(StoreBB, DL, TII->get(CMPri)) in ExpandCMP_SWAP_64()
H A DARMScheduleR52.td332 def : InstRW<[R52WriteCC, R52Read_EX1], (instregex "CMPri", "CMNri")>;
H A DARMBaseInstrInfo.cpp2802 case ARM::CMPri: in analyzeCompare()
2892 if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) && in isRedundantFlagInstr()
3053 if (CmpInstr.getOpcode() == ARM::CMPri || in optimizeCompareInstr()
H A DARMFastISel.cpp1407 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri; in ARMEmitCmp()
H A DARMInstrInfo.td4887 (CMPri GPR:$src, mod_imm:$imm)>;
6348 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
H A DARMISelLowering.cpp10940 BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) in EmitSjLjDispatchBlock()
11996 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) in EmitInstrWithCustomInserter()
12000 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) in EmitInstrWithCustomInserter()
12088 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) in EmitInstrWithCustomInserter()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstr64Bit.td179 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
H A DSparcInstrInfo.td811 def CMPri : F3_2<2, 0b010100,