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Searched refs:CLC (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/libclc/cmake/
H A DCMakeTestCLCCompiler.cmake15 # determine that that selected CLC compiler can actually compile
20 PrintTestCompilerStatus("CLC" "")
36 PrintTestCompilerStatus("CLC" " -- broken")
38 "Determining if the CLC compiler works failed with "
40 message(FATAL_ERROR "The CLC compiler \"${CMAKE_CLC_COMPILER}\" "
46 PrintTestCompilerStatus("CLC" " -- works")
48 "Determining if the CLC compiler works passed with "
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dmemcmp-02.ll1 ; Test memcmp using CLC. In this test case the CLC loop will do all the work
H A Dmemcmp-nobuiltin.ll1 ; Test that memcmp won't be converted to CLC if calls are
103 ; Check the upper end of the CLC range. Here the result is used both as
H A Dmemcmp-01.ll1 ; Test memcmp using CLC, with i32 results.
103 ; Check the upper end of the CLC range. Here the result is used both as
/llvm-project-15.0.7/clang/test/Preprocessor/
H A Dmacro_variadic.cl3 // RUN: %clang_cc1 -verify %s -cl-std=CLC++
4 // RUN: %clang_cc1 -verify %s -pedantic -cl-std=CLC++
/llvm-project-15.0.7/clang/test/Misc/
H A Dnvptx.unsupported_core.cl3 // RUN: %clang_cc1 -cl-std=CLC++ -triple nvptx-unknown-unknown -Wpedantic-core-features %s 2> %t
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DLangStandards.def199 LANGSTANDARD_ALIAS_DEPR(openclcpp10, "CLC++")
200 LANGSTANDARD_ALIAS_DEPR(openclcpp10, "CLC++1.0")
201 LANGSTANDARD_ALIAS_DEPR(openclcpp2021, "CLC++2021")
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp27 SDVTList VTs = Op == SystemZISD::CLC ? DAG.getVTList(MVT::i32, MVT::Other) in createMemMemNode()
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
H A DREADME.txt39 We only use MVC, XC and CLC for constant-length block operations.
H A DSystemZISelLowering.h127 CLC, enumerator
H A DSystemZOperators.td418 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLengthCC,
H A DSystemZISelLowering.cpp5943 OPCODE(CLC); in getTargetNodeName()
8254 if (Opcode == SystemZ::CLC) { in emitMemMemWrapper()
8279 (Opcode == SystemZ::CLC && (ImmLength > 256 || NeedsLoop) in emitMemMemWrapper()
9001 return emitMemMemWrapper(MI, MBB, SystemZ::CLC); in EmitInstrWithCustomInserter()
H A DSystemZScheduleZ196.td526 def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "CLC$")>;
H A DSystemZScheduleZEC12.td536 def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "CLC$")>;
H A DSystemZScheduleZ13.td564 def : InstRW<[WLat6, FXb, LSU2, Cracked], (instregex "CLC$")>;
/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-family-set-clr-flag.s42 ; CLC
/llvm-project-15.0.7/clang/test/SemaOpenCL/
H A Dfdeclare-opencl-builtins.cl8 // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC…
9 // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC…
10 // RUN: %clang_cc1 %s -triple spir -verify -pedantic -Wconversion -Werror -fsyntax-only -cl-std=CLC…
/llvm-project-15.0.7/clang/test/Parser/
H A Dopencl-atomics-cl20.cl4 // RUN: %clang_cc1 %s -triple spir64-unknown-unknown -verify -fsyntax-only -cl-std=CLC++
/llvm-project-15.0.7/libclc/
H A DCMakeLists.txt143 enable_language( CLC LLAsm )
332 LINKER_LANGUAGE CLC )
/llvm-project-15.0.7/clang/docs/
H A DUsersManual.rst3449 - C++ for OpenCL 1.0: ``-cl-std=clc++``, ``-cl-std=CLC++``, ``-cl-std=clc++1.0``,
3450 ``-cl-std=CLC++1.0``, ``-std=clc++``, ``-std=CLC++``, ``-std=clc++1.0`` or
3451 ``-std=CLC++1.0``.
3453 - C++ for OpenCL 2021: ``-cl-std=clc++2021``, ``-cl-std=CLC++2021``,
3454 ``-std=clc++2021``, ``-std=CLC++2021``.
H A DClangCommandLineReference.rst2871 ….2', 'cl2.0', 'CL2.0', 'cl3.0', 'CL3.0', 'clc++', 'CLC++', 'clc++1.0', 'CLC++1.0', 'clc++2021' or …
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td1140 def: InstRW<[WriteZero], (instrs CLC)>;
H A DX86SchedSkylakeClient.td1772 def: InstRW<[WriteZero], (instrs CLC)>;
H A DX86SchedBroadwell.td1622 def: InstRW<[WriteZero], (instrs CLC)>;
H A DX86SchedHaswell.td1881 def: InstRW<[WriteZero], (instrs CLC)>;

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