| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 162 static SDValue addIPMSequence(const SDLoc &DL, SDValue CCReg, in addIPMSequence() argument
164 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); in addIPMSequence()
176 SDValue CCReg; in EmitTargetCodeForMemcmp() local
181 CCReg = emitMemMemImm(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Bytes); in EmitTargetCodeForMemcmp()
183 CCReg = emitMemMemReg(DAG, DL, SystemZISD::CLC, Chain, Src2, Src1, Size); in EmitTargetCodeForMemcmp()
184 Chain = CCReg.getValue(1); in EmitTargetCodeForMemcmp()
185 return std::make_pair(addIPMSequence(DL, CCReg, DAG), Chain); in EmitTargetCodeForMemcmp()
201 SDValue CCReg = End.getValue(1); in EmitTargetCodeForMemchr() local
209 DAG.getTargetConstant(SystemZ::CCMASK_SRST_FOUND, DL, MVT::i32), CCReg}; in EmitTargetCodeForMemchr()
232 SDValue CCReg = Unused.getValue(1); in EmitTargetCodeForStrcmp() local
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| H A D | SystemZISelLowering.cpp | 3111 SDValue CCReg = emitCmp(DAG, DL, C); in lowerSETCC() local
3131 SDValue CCReg = emitCmp(DAG, DL, C); in lowerSTRICT_FSETCC() local
3132 CCReg->setFlags(Op->getFlags()); in lowerSTRICT_FSETCC()
3146 SDValue CCReg = emitCmp(DAG, DL, C); in lowerBR_CC() local
3200 SDValue CCReg = emitCmp(DAG, DL, C); in lowerSELECT_CC() local
4440 SDLoc DL(CCReg); in getCCResult()
6907 auto *ICmp = CCReg.getNode(); in combineCCMask()
6977 CCReg = IPM->getOperand(0); in combineCCMask()
6997 SDValue CCReg = N->getOperand(4); in combineBR_CCMASK() local
7020 SDValue CCReg = N->getOperand(4); in combineSELECT_CCMASK() local
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| H A D | SystemZISelDAGToDAG.cpp | 1894 SDValue CCReg = Node->getOperand(4); in expandSelectBoolean() local
1896 SDValue Result = CurDAG->getNode(SystemZISD::IPM, DL, MVT::i32, CCReg); in expandSelectBoolean()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 180 Register CCReg = CC->getReg(); in optimizeVcndVcmpPair() local
184 if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And)) in optimizeVcndVcmpPair()
205 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg()); in optimizeVcndVcmpPair()
220 if (CCReg.isVirtual()) { in optimizeVcndVcmpPair()
241 LiveInterval &CCLI = LIS->getInterval(CCReg); in optimizeVcndVcmpPair()
263 LIS->removeAllRegUnitsForPhysReg(CCReg); in optimizeVcndVcmpPair()
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| H A D | AMDGPUInstructionSelector.cpp | 1106 Register CCReg = I.getOperand(0).getReg(); in selectG_ICMP() local
1107 if (!isVCC(CCReg, *MRI)) { in selectG_ICMP()
1114 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg) in selectG_ICMP()
1118 RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_ICMP()
1859 Register CCReg = CCOp.getReg(); in selectG_SELECT() local
1860 if (!isVCC(CCReg, *MRI)) { in selectG_SELECT()
1864 .addReg(CCReg); in selectG_SELECT()
1869 if (!MRI->getRegClassOrNull(CCReg)) in selectG_SELECT()
1870 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCInstPrinter.cpp | 492 unsigned CCReg = MI->getOperand(OpNo).getReg(); in printcrbitm() local
494 switch (CCReg) { in printcrbitm()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 549 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
550 return MachineOperand::CreateReg(CCReg, false);
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| H A D | ARMConstantIslandPass.cpp | 1748 Register CCReg = MI->getOperand(2).getReg(); in fixupConditionalBr() local
1805 .addMBB(NextBB).addImm(CC).addReg(CCReg); in fixupConditionalBr()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4427 SDValue CCReg = SelectCC(LHS, RHS, CC, dl, Chain); in trySETCC() local
4429 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), CCReg.getValue(1)); in trySETCC()
4442 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, in trySETCC()
4446 CCReg), 0); in trySETCC()
5591 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); in Select() local
5607 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
5655 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), in Select()
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