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Searched refs:CCOp (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td215 def CCOp : Operand<i32>;
909 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
1470 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1476 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1485 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1490 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1499 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1504 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1518 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1523 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
[all …]
H A DSparcInstr64Bit.td325 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
330 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
338 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
343 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
349 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td231 def CCOp : Operand<i32> {
685 def BRCC : InstBR<(outs), (ins BrTarget:$addr, CCOp:$DDDI),
768 def SCC : InstSCC<(outs GPR:$Rs1), (ins CCOp:$DDDI),
776 (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
788 def BRIND_CC : InstRR<0b101, (outs), (ins GPR:$Rs1, CCOp:$DDDI),
796 def BRIND_CCA : InstRR<0b101, (outs), (ins GPR:$Rs1, GPR:$Rs2, CCOp:$DDDI),
808 def BRR : InstBRR<(outs), (ins i16imm:$imm16, CCOp:$DDDI),
H A DLanaiISelLowering.cpp1428 SDValue CCOp; in combineSelectAndUse() local
1430 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
1442 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal); in combineSelectAndUse()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrInfo.td405 def CCOpAsmOperand : AsmOperandClass { let Name = "CCOp"; }
406 def CCOp : Operand<i32>, ImmLeaf<i32, [{
487 // Note that these values must be kept in sync with the CCOp::CondCode enum
723 (ins CCOp:$cfw, simm7:$sy, I64:$sz, I64:$sd),
727 (ins CCOp:$cfw, RC:$sy, mimm:$sz, I64:$sd),
731 (ins CCOp:$cfw, simm7:$sy, mimm:$sz, I64:$sd),
831 defm r : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, RC:$comp)>;
833 defm i : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, immOp:$comp)>;
860 defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy,
863 defm rz : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy,
[all …]
H A DVEInstrVec.td60 (ins CCOp:$cf, V64:$vz, I32:$vl),
63 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
66 (ins CCOp:$cf, V64:$vz, I32:$vl),
69 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl),
766 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>;
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrInfo.td21 def CCOp : PredicateOperand<i32, (ops i32imm), (ops)>;
403 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
407 (outs GPR32:$B), (ins u6:$C, CCOp:$cc, GPR32:$B2),
/llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp190 struct CCOp { struct in __anone15613a60211::VEOperand
208 struct CCOp CC;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp310 bool Negate, Register CCOp,
4850 Register Val, AArch64CC::CondCode &OutCC, bool Negate, Register CCOp, in emitConjunctionRec() argument
4872 if (!CCOp) in emitConjunctionRec()
4877 CCOp = ExtraCmp->getOperand(0).getReg(); in emitConjunctionRec()
4883 if (!CCOp) { in emitConjunctionRec()
4953 emitConjunctionRec(RHS, RHSCC, NegateR, CCOp, Predicate, MIB); in emitConjunctionRec()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp1858 const MachineOperand &CCOp = I.getOperand(1); in selectG_SELECT() local
1859 Register CCReg = CCOp.getReg(); in selectG_SELECT()
1870 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp3697 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get(); in ExpandNode() local
3699 if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) { in ExpandNode()
3717 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp, Tmp1.getValueType()); in ExpandNode()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2991 ISD::CondCode CC, SDValue CCOp, in emitConditionalComparison() argument
3020 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); in emitConditionalComparison()
3100 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, in emitConjunctionRec() argument
3123 if (!CCOp.getNode()) in emitConjunctionRec()
3126 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, in emitConjunctionRec()
3128 CCOp = ExtraCmp; in emitConjunctionRec()
3134 if (!CCOp) in emitConjunctionRec()
3137 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL, in emitConjunctionRec()
3198 SDValue CmpR = emitConjunctionRec(DAG, RHS, RHSCC, NegateR, CCOp, Predicate); in emitConjunctionRec()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp786 struct CCOp { struct in __anon2aa686d00111::ARMOperand
909 struct CCOp CC;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12357 SDValue CCOp; in combineSelectAndUse() local
12359 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps, in combineSelectAndUse()
12372 CCOp, TrueVal, FalseVal); in combineSelectAndUse()