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Searched refs:BFE (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dshift-and-i64-ubfe.ll4 ; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half.
43 ; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1
45 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
61 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
95 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO1]]]
111 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
127 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
179 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO1]]]
214 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO1]]]
262 ; GCN: buffer_store_dword [[BFE]]
[all …]
H A Dbfe-combine.ll6 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 8, 8
7 ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], 2, v[[BFE]]
27 ; VI: v_bfe_u32 v[[BFE:[0-9]+]], v{{[0-9]+}}, 16, 16
28 ; VI: v_lshlrev_b32_e32 v[[ADDRBASE:[0-9]+]], {{[^,]+}}, v[[BFE]]
H A Dsext-eliminate.ll8 ; EG-NOT: BFE
20 ; EG-NOT: BFE
H A Dsext-in-reg.ll262 ; EG-NOT: BFE
283 ; EG-NOT: BFE
524 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x10000
525 ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
543 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000
544 ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
563 ; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]]
584 ; GCN: ds_write_b16 v{{[0-9]+}}, [[BFE]]
604 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000
605 ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
[all …]
H A Dbfe-patterns.ll28 ; GCN-NEXT: v_lshrrev_b32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
30 ; GCN: [[BFE]]
102 ; GCN-NEXT: v_ashrrev_i32_e32 [[BFE:v[0-9]+]], [[SUB]], [[SHL]]
104 ; GCN: [[BFE]]
H A Dsint_to_fp.f64.ll78 ; VI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x80000
79 ; VI: s_sext_i32_i16 [[SEXT:s[0-9]+]], [[BFE]]
H A Dsext-in-reg-failure-r600.ll5 ; EG-NOT: BFE
H A Dllvm.amdgcn.ubfe.ll1039 ; EG-NOT: BFE
1065 ; EG-NOT: BFE
1091 ; EG-NOT: BFE
1117 ; EG-NOT: BFE
1143 ; EG-NOT: BFE
1169 ; EG-NOT: BFE
1195 ; EG-NOT: BFE
1221 ; EG-NOT: BFE
1247 ; EG-NOT: BFE
1273 ; EG-NOT: BFE
[all …]
H A Dllvm.amdgcn.sbfe.ll384 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 0, 24
385 ; GCN: buffer_store_dword [[BFE]],
397 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16
398 ; GCN: v_lshrrev_b32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]]
399 ; GCN: v_add_{{[iu]}}32_e32 [[TMP1:v[0-9]+]], vcc, [[TMP0]], [[BFE]]
456 ; Make sure there isn't a redundant BFE
H A Dcgp-bitfield-extract.ll123 ; VI: s_bfe_u32 [[BFE:s[0-9]+]], [[ARG]], 0xc0004
157 ; 32-bit BFE on one half of the integer.
H A Dshift-i64-opts.ll59 ; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[LO]], 8, 23
60 ; GCN: buffer_store_dwordx2 v[[[BFE]]:[[ZERO]]]
H A Dload-constant-i1.ll233 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
234 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
H A Dload-global-i1.ll233 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
234 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
H A Dload-local-i1.ll295 ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
296 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
H A Dkernel-argument-dag-lowering.ll137 ; GCN-DAG: s_bfe_u32 [[BFE:s[0-9]+]], [[DWORD]], 0x100010{{$}}
H A Dload-constant-i16.ll950 ; TODO: We should use ASHR instead of LSHR + BFE
1285 ; TODO: We should use ASHR instead of LSHR + BFE
H A Dload-global-i16.ll1248 ; TODO: This should use ASHR instead of LSHR + BFE
1695 ; TODO: We should use ASHR instead of LSHR + BFE
/llvm-project-15.0.7/clang/lib/Basic/
H A DFileManager.cpp515 FileEntry *BFE = new (FilesAlloc.Allocate()) FileEntry(); in getBypassFile() local
516 BypassFileEntries.push_back(BFE); in getBypassFile()
517 Insertion.first->second = FileEntryRef::MapValue(*BFE, VF.getDir()); in getBypassFile()
518 BFE->LastRef = FileEntryRef(*Insertion.first); in getBypassFile()
519 BFE->Size = Status.getSize(); in getBypassFile()
520 BFE->Dir = VF.getFileEntry().Dir; in getBypassFile()
521 BFE->ModTime = llvm::sys::toTimeT(Status.getLastModificationTime()); in getBypassFile()
522 BFE->UID = NextFileUID++; in getBypassFile()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-intrinsics.ll1043 ; CHECK-NEXT: ret i32 [[BFE]]
1052 ; CHECK-NEXT: ret i32 [[BFE]]
1061 ; CHECK-NEXT: ret i32 [[BFE]]
1078 ; CHECK-NEXT: ret i32 [[BFE]]
1095 ; CHECK-NEXT: ret i32 [[BFE]]
1104 ; CHECK-NEXT: ret i32 [[BFE]]
1113 ; CHECK-NEXT: ret i32 [[BFE]]
1122 ; CHECK-NEXT: ret i32 [[BFE]]
1131 ; CHECK-NEXT: ret i32 [[BFE]]
1158 ; CHECK-NEXT: ret i32 [[BFE]]
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1424 // BFE - bit-field extract
1427 // Template for BFE instructions. Takes four args,
1433 multiclass BFE<string TyStr, RegisterClass RC> {
1449 defm BFE_S32 : BFE<"s32", Int32Regs>;
1450 defm BFE_U32 : BFE<"u32", Int32Regs>;
1451 defm BFE_S64 : BFE<"s64", Int64Regs>;
1452 defm BFE_U64 : BFE<"u64", Int64Regs>;
/llvm-project-15.0.7/bolt/lib/Rewrite/
H A DRewriteInstance.cpp1427 BFE = BC->getBinaryFunctions().end(); in adjustFunctionBoundaries() local
1428 BFI != BFE; ++BFI) { in adjustFunctionBoundaries()
1431 if (std::next(BFI) != BFE) in adjustFunctionBoundaries()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.sbfe.ll818 ; Make sure there isn't a redundant BFE
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp2118 const unsigned BFE = Signed ? AMDGPU::V_BFE_I32_e64 : AMDGPU::V_BFE_U32_e64; in selectG_SZA_EXT() local
2120 BuildMI(MBB, I, DL, TII.get(BFE), DstReg) in selectG_SZA_EXT()
H A DSIISelLowering.cpp9604 SDValue BFE = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32, in performAndCombine() local
9609 SDValue Ext = DAG.getNode(ISD::AssertZext, SL, VT, BFE, in performAndCombine()