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/llvm-project-15.0.7/llvm/test/Transforms/Attributor/
H A Dchain.ll13 ; CHECK_1-NEXT: [[BC1:%.*]] = bitcast i32* [[ARG]] to i8*
14 ; CHECK_1-NEXT: call void @foo(i8* noundef dereferenceable_or_null(8) [[BC1]])
21 ; CHECK_5-NEXT: [[BC1:%.*]] = bitcast i32* [[ARG]] to i8*
22 ; CHECK_5-NEXT: call void @foo(i8* noundef nonnull dereferenceable(8) [[BC1]])
H A Dreturned.ll913 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
916 ; CHECK-NEXT: [[PHI:%.*]] = phi double* [ [[BC1]], [[IF_THEN]] ], [ [[BC0]], [[ENTRY:%.*]] ]
963 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
964 ; CHECK-NEXT: ret double* [[BC1]]
1017 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i32* [[B]] to double*
1018 ; CHECK-NEXT: ret double* [[BC1]]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/
H A Dshuffle-inseltpoison.ll167 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4…
183 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4…
231 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2…
232 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i…
247 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2…
248 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i…
263 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <4 x i32>
264 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i…
279 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <8 x i16> [[SHUFFLE1]] to <4 x i32>
280 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i…
[all …]
H A Dshuffle.ll167 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4…
183 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4…
231 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2…
232 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i3…
247 ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2…
248 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i3…
263 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <4 x i32>
264 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i3…
279 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <8 x i16> [[SHUFFLE1]] to <4 x i32>
280 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i3…
[all …]
/llvm-project-15.0.7/llvm/test/tools/gold/X86/
H A Dparallel.ll5 ; RUN: llvm-dis %t.1.5.precodegen.bc -o - | FileCheck --check-prefix=CHECK-BC1 %s
22 ; CHECK-BC1: declare dso_local void @foo
23 ; CHECK-BC1: define dso_local void @bar
H A Dthinlto-emit-llvm.ll4 ; RUN: llvm-dis %t.bc1 -o - | FileCheck --check-prefix=CHECK-BC1 %s
10 ; CHECK-BC1: define dso_local i32 @_Z3foov()
/llvm-project-15.0.7/llvm/test/tools/gold/X86/v1.12/
H A Dthinlto_emit_linked_objects.ll36 ; RUN: llvm-bcanalyzer --dump %t1.o.thinlto.bc | FileCheck %s -check-prefixes=CHECK-BC1
37 ; CHECK-BC1: <GLOBALVAL_SUMMARY_BLOCK
38 ; CHECK-BC1: <FLAGS op0=[[#]]/>
39 ; CHECK-BC1: </GLOBALVAL_SUMMARY_BLOCK
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/X86/
H A Dshuffle-inseltpoison.ll96 ; SSE-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <16 x i8>
97 ; SSE-NEXT: [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
106 ; AVX-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 12…
107 ; AVX-NEXT: [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
127 ; SSE-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <8 x i16>
128 ; SSE-NEXT: [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
137 ; AVX-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 6, …
138 ; AVX-NEXT: [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
H A Dshuffle.ll96 ; SSE-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <16 x i8>
97 ; SSE-NEXT: [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
106 ; AVX-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 12…
107 ; AVX-NEXT: [[ADD:%.*]] = shl <16 x i8> [[BC1]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1…
127 ; SSE-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[PERMIL]] to <8 x i16>
128 ; SSE-NEXT: [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
137 ; AVX-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 6, …
138 ; AVX-NEXT: [[ADD:%.*]] = shl <8 x i16> [[BC1]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 …
/llvm-project-15.0.7/llvm/tools/llvm-cov/
H A DCoverageExporterLcov.cpp143 unsigned BC1 = NextBranch->ExecutionCount; in renderBranchExecutionCounts() local
145 bool BranchNotExecuted = (BC1 == 0 && BC2 == 0); in renderBranchExecutionCounts()
153 OS << ',' << (I == 0 ? BC1 : BC2) << '\n'; in renderBranchExecutionCounts()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dreduction-odd-interleave-counts.ll20 ; UF3-NEXT: [[BC1:%.+]] = bitcast i32* [[L_GEP1]] to <4 x i32>*
21 ; UF3-NEXT: [[L1:%.+]] = load <4 x i32>, <4 x i32>* [[BC1]], align 4
59 ; UF5-NEXT: [[BC1:%.+]] = bitcast i32* [[L_GEP1]] to <4 x i32>*
60 ; UF5-NEXT: [[L1:%.+]] = load <4 x i32>, <4 x i32>* [[BC1]], align 4
/llvm-project-15.0.7/llvm/test/Transforms/ConstantHoisting/AArch64/
H A Dconst-hoist-gep.ll10 ; CHECK-NEXT: %[[BC1:[a-z0-9_]+]] = bitcast i32* %const to i8*
11 ; CHECK-NEXT: %[[M1:[a-z0-9_]+]] = getelementptr i8, i8* %[[BC1]], i32 4
/llvm-project-15.0.7/llvm/test/Transforms/ConstantHoisting/ARM/
H A Dconst-hoist-gep.ll12 ; CHECK-NEXT: %[[BC1:[a-z0-9_]+]] = bitcast i32* %[[C2]] to i8*
13 ; CHECK-NEXT: %[[M1:[a-z0-9_]+]] = getelementptr i8, i8* %[[BC1]], i32 4
/llvm-project-15.0.7/clang/test/Driver/
H A Dhip-binding.hip20 // RDCS: # "amdgcn-amd-amdhsa" - "clang", inputs: ["[[IN:.*hip-binding.hip]]"], output: "[[BC1:.*bc…
23 // RDCS: # "x86_64-unknown-linux-gnu" - "offload bundler", inputs: ["[[BC1]]", "[[BC2]]", "[[HOSTOB…
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbitcast.ll181 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x float> [[A:%.*]] to <2 x i64>
184 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i64> [[BC2]], [[BC1]]
200 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i128 [[A:%.*]] to <2 x i64>
201 ; CHECK-NEXT: [[OR:%.*]] = or <2 x i64> [[BC1]], [[B:%.*]]
215 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[A:%.*]] to i128
216 ; CHECK-NEXT: [[XOR:%.*]] = xor i128 [[BC1]], [[B:%.*]]
463 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <1 x i64> [[A:%.*]] to <1 x double>
464 ; CHECK-NEXT: [[BC:%.*]] = extractelement <1 x double> [[BC1]], i64 0
474 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <1 x i64> [[A:%.*]] to <1 x double>
475 ; CHECK-NEXT: [[BC:%.*]] = extractelement <1 x double> [[BC1]], i64 0
H A Dload-bitcast-select.ll59 ; CHECK-NEXT: [[BC1:%.*]] = bitcast float* [[SEL]] to i32*
60 ; CHECK-NEXT: [[LD:%.*]] = load i32, i32* [[BC1]], align 4
H A Dbitcast-inseltpoison.ll151 ; CHECK-NEXT: [[BC1:%.*]] = bitcast i128 [[A:%.*]] to <2 x i64>
152 ; CHECK-NEXT: [[OR:%.*]] = or <2 x i64> [[BC1]], [[B:%.*]]
166 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[A:%.*]] to i128
167 ; CHECK-NEXT: [[XOR:%.*]] = xor i128 [[BC1]], [[B:%.*]]
H A Dlogical-select-inseltpoison.ll345 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[SEXT]] to <2 x i64>
346 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[BC1]], [[A:%.*]]
623 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
624 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[SIA]], [[BC1]]
H A Dlogical-select.ll346 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[SEXT]] to <2 x i64>
347 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[BC1]], [[A:%.*]]
655 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x double> [[A]] to <2 x i64>
656 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[SIA]], [[BC1]]
H A Dtrunc.ll557 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x i64> [[V:%.*]] to <4 x i32>
558 ; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x i32> [[BC1]], i64 2
H A Dtrunc-inseltpoison.ll557 ; CHECK-NEXT: [[BC1:%.*]] = bitcast <2 x i64> [[V:%.*]] to <4 x i32>
558 ; CHECK-NEXT: [[EXT:%.*]] = extractelement <4 x i32> [[BC1]], i64 2
H A Dselect.ll817 ; CHECK-NEXT: [[BC1:%.*]] = trunc <4 x i64> [[A:%.*]] to <4 x i32>
819 ; CHECK-NEXT: [[SEL1:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[BC1]], <4 x i32> [[BC2]]
820 ; CHECK-NEXT: [[SEL2:%.*]] = select <4 x i1> [[CMP]], <4 x i32> [[BC2]], <4 x i32> [[BC1]]
/llvm-project-15.0.7/llvm/test/Transforms/WholeProgramDevirt/
H A Dimport.ll39 ; VCP: [[BC1:%.*]] = bitcast i8* [[GEP1]] to i32*
40 ; VCP: [[LOAD1:%.*]] = load i32, i32* [[BC1]]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp6933 Value *BC1 = Builder.CreateBitCast( in optimizeShuffleVectorInst() local
6935 Value *Shuffle = Builder.CreateVectorSplat(NewVecType->getNumElements(), BC1); in optimizeShuffleVectorInst()
6944 if (auto *BCI = dyn_cast<Instruction>(BC1)) in optimizeShuffleVectorInst()
/llvm-project-15.0.7/llvm/lib/IR/
H A DAutoUpgrade.cpp3993 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); in UpgradeIntrinsicCall() local
3995 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); in UpgradeIntrinsicCall()

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