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Searched refs:B64 (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dcl20-device-side-enqueue.cl58 // B64: %[[BLOCK_SIZES1:.*]] = alloca [1 x i64]
130 // B64: store i64 256, i64* %[[TMP]], align 8
136 // B64-SAME: i64* %[[TMP]])
161 // B64-SAME: i64* %[[TMP]])
182 // B64: store i64 256, i64* %[[TMP]], align 8
188 // B64-SAME: i64* %[[TMP]])
215 // B64-SAME: i64* %[[TMP]])
240 // B64-SAME: i64* %[[TMP]])
262 // B64: store i64 1, i64* %[[TMP]], align 8
272 // B64-SAME: i64* %[[TMP]])
[all …]
/llvm-project-15.0.7/compiler-rt/test/cfi/
H A Dcreate-derivers.test14 …lowertypetests -debug-only=lowertypetests -o /dev/null %t3.o 2>&1 | FileCheck --check-prefix=B64 %s
15 B64: {{1B|B@@}}: {{.*}} size 5{{3|4}}
16 B64-NOT: all-ones
H A DREADME.txt7 - B64 forces 64-bit bit sets.
H A Dutils.h58 #ifdef B64
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULibFunc.h257 B64 = 4, enumerator
266 U64 = UINT | B64,
270 I64 = INT | B64,
273 F64 = FLOAT | B64,
H A DSIRegisterInfo.td966 let ParserMatchClass = RegImmMatcher<MatchName#"B64">;
H A DSIInstructions.td1610 // FIXME: Use S_BITSET0_B32/B64?
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A D32-bit-local-address-space.ll11 ; instructions with B64, U64, and I64 take 64-bit operands.
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s1935737938.ll111 %B64 = and i8 %Sl44, -69
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1033 CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_8, M8, B64) in Select()
1093 CASE_VMSLT_OPCODES(LMUL_8, M8, B64) in Select()
H A DRISCVInstrInfoVPseudos.td314 def : MTypeInfo<vbool1_t, V_M8, "B64">;
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dfunnel_shift.ll26 ; CHECK-NEXT: [[I64:%.*]] = call i64 @llvm.fshl.i64(i64 [[A64:%.*]], i64 [[B64:%.*]], i64 [[C64]…