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Searched refs:B32 (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Dcl20-device-side-enqueue.cl128 // B32: store i32 256, i32* %[[TMP]], align 4
135 // B32-SAME: i32* %[[TMP]])
160 // B32-SAME: i32* %[[TMP]])
180 // B32: store i32 256, i32* %[[TMP]], align 4
187 // B32-SAME: i32* %[[TMP]])
214 // B32-SAME: i32* %[[TMP]])
239 // B32-SAME: i32* %[[TMP]])
256 // B32: store i32 1, i32* %[[TMP]], align 4
271 // B32-SAME: i32* %[[TMP]])
288 // B32: store i32 0, i32* %[[TMP]], align 4
[all …]
/llvm-project-15.0.7/compiler-rt/test/cfi/
H A Dcreate-derivers.test9 …lowertypetests -debug-only=lowertypetests -o /dev/null %t2.o 2>&1 | FileCheck --check-prefix=B32 %s
10 B32: {{1B|B@@}}: {{.*}} size 2{{3|4}}
11 B32-NOT: all-ones
H A DREADME.txt6 - B32 forces 32-bit bit sets.
H A Dutils.h54 #ifdef B32
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULibFunc.h256 B32 = 3, enumerator
265 U32 = UINT | B32,
269 I32 = INT | B32,
272 F32 = FLOAT | B32,
H A DSIRegisterInfo.td937 let ParserMatchClass = RegImmMatcher<MatchName#"B32">;
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll57 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
58 ; CHECK-NOF16-NEXT: add.rn.f32 [[R32:%f[0-9]+]], [[A32]], [[B32]];
73 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
90 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
106 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
122 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
155 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
735 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
753 ; XCHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
948 ; CHECK-NOF16-DAG: cvt.f32.f16 [[B32:%f[0-9]+]], [[B]]
[all …]
/llvm-project-15.0.7/clang/test/SemaOpenCL/
H A Dcl20-device-side-enqueue.cl89 #ifdef B32
109 #ifdef B32
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A D32-bit-local-address-space.ll10 ; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1032 CASE_VMSLT_VMNAND_VMSET_OPCODES(LMUL_4, M4, B32) in Select()
1092 CASE_VMSLT_OPCODES(LMUL_4, M4, B32) in Select()
H A DRISCVInstrInfoVPseudos.td313 def : MTypeInfo<vbool2_t, V_M4, "B32">;
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dfunnel_shift.ll70 ; CHECK-NEXT: [[I32:%.*]] = call i32 @llvm.fshl.i32(i32 [[A32:%.*]], i32 [[B32:%.*]], i32 [[C32]…
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-add-saddo.ll707 ; CHECK-NEXT: [[B32:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A32]], i8 [[B32]])
H A Darith-add-uaddo.ll707 ; CHECK-NEXT: [[B32:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A32]], i8 [[B32]])
H A Darith-mul-umulo.ll707 ; CHECK-NEXT: [[B32:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A32]], i8 [[B32]])
H A Darith-mul-smulo.ll707 ; CHECK-NEXT: [[B32:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A32]], i8 [[B32]])
H A Darith-sub-ssubo.ll707 ; CHECK-NEXT: [[B32:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A32]], i8 [[B32]])
H A Darith-sub-usubo.ll707 ; CHECK-NEXT: [[B32:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
771 ; CHECK-NEXT: [[C32:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A32]], i8 [[B32]])
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/misc/ConfusableTable/
H A Dconfusables.txt9511 2FC0 ; 9B32 ; MA #* ( ⿀ → 鬲 ) KANGXI RADICAL CAULDRON → CJK UNIFIED IDEOGRAPH-9B32 #