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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvbinop-simplify-bug.ll20 %B23 = sub <8 x i32> %Shuff, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
21 ret <8 x i32> %B23
H A Dfold-vector-shuffle-crash.ll57 %B23 = sub i64 419346, %4
60 %Cmp26 = icmp ugt i64 %B, %B23
163 %I97 = insertelement <4 x i64> zeroinitializer, i64 %B23, i32 1
336 %Sl226 = select i1 %Cmp93, i64 %E28, i64 %B23
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dlatticeval-invalidate.ll19 %B23 = lshr i64 %B8, undef
28 %B15 = sub i64 %B8, %B23
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/msa/
H A Dllvm-stress-s525530439.ll51 %B23 = shl i32 71140, 439732
63 %Sl31 = select i1 %Cmp18, i32 %3, i32 %B23
133 store i32 %B23, i32* %PC
H A Dllvm-stress-s3861334421.ll53 %B23 = fdiv double %Sl17, 0.000000e+00
124 %B68 = frem double %B23, %Sl17
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h153 case AArch64::D23: return AArch64::B23; in getBRegFromDReg()
193 case AArch64::B23: return AArch64::D23; in getDRegFromBReg()
/llvm-project-15.0.7/clang/test/Misc/
H A Ddiag-template-diffing.cpp591 typedef const C23<int> B23; typedef
592 template<class ...T> using A23 = B23;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td283 def B23 : AArch64Reg<23, "b23">, DwarfRegNum<[87]>;
317 def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>;
352 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>;
387 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
422 def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/ParallelDSP/
H A Dunroll-n-jam-smlad.ll189 %B23 = load i16, i16* %arrayidx4.us.i.1.3.i, align 2
190 %conv.us.i.1.3.i = sext i16 %B23 to i32
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/X86/
H A Dextract-binop.ll466 ; CHECK-NEXT: [[B23:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
469 ; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[B23]], i32 3
H A Dextract-binop-inseltpoison.ll466 ; CHECK-NEXT: [[B23:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
469 ; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[B23]], i32 3
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp257 {codeview::RegisterId::ARM64_B23, AArch64::B23}, in initLLVMToCVRegMapping()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshift.ll1782 %B23 = mul i32 %B15, %B
1795 %B11 = or i32 0, %B23
H A Dand-or-icmps.ll394 %B23 = mul i16 %B11, %B11
398 %B18 = mul i16 %B23, %B7
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Darith-add-saddo.ll339 ; CHECK-NEXT: [[B23:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.sadd.with.overflow.i16(i16 [[A23]], i16 [[B23…
698 ; CHECK-NEXT: [[B23:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 [[A23]], i8 [[B23]])
H A Darith-add-uaddo.ll339 ; CHECK-NEXT: [[B23:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 [[A23]], i16 [[B23…
698 ; CHECK-NEXT: [[B23:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.uadd.with.overflow.i8(i8 [[A23]], i8 [[B23]])
H A Darith-mul-umulo.ll339 ; CHECK-NEXT: [[B23:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.umul.with.overflow.i16(i16 [[A23]], i16 [[B23…
698 ; CHECK-NEXT: [[B23:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[A23]], i8 [[B23]])
H A Darith-mul-smulo.ll339 ; CHECK-NEXT: [[B23:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.smul.with.overflow.i16(i16 [[A23]], i16 [[B23…
698 ; CHECK-NEXT: [[B23:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.smul.with.overflow.i8(i8 [[A23]], i8 [[B23]])
H A Darith-sub-ssubo.ll339 ; CHECK-NEXT: [[B23:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.ssub.with.overflow.i16(i16 [[A23]], i16 [[B23…
698 ; CHECK-NEXT: [[B23:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 [[A23]], i8 [[B23]])
H A Darith-sub-usubo.ll339 ; CHECK-NEXT: [[B23:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16,…
371 ; CHECK-NEXT: [[C23:%.*]] = call { i16, i1 } @llvm.usub.with.overflow.i16(i16 [[A23]], i16 [[B23…
698 ; CHECK-NEXT: [[B23:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @b8, i32 …
762 ; CHECK-NEXT: [[C23:%.*]] = call { i8, i1 } @llvm.usub.with.overflow.i8(i8 [[A23]], i8 [[B23]])