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Searched refs:ArgVT (Results 1 – 25 of 34) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp87 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments() local
89 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) in AnalyzeFormalArguments()
127 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands() local
129 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeCallOperands()
132 << EVT(ArgVT).getEVTString() << '\n'; in AnalyzeCallOperands()
145 MVT ArgVT = ArgVTs[i]; in AnalyzeCallOperands() local
147 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeCallOperands()
150 << EVT(ArgVT).getEVTString() << '\n'; in AnalyzeCallOperands()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h42 bool IsShortVectorType(EVT ArgVT) { in IsShortVectorType() argument
43 return ArgVT.isVector() && ArgVT.getStoreSize() <= 8; in IsShortVectorType()
60 ArgIsShortVector.push_back(IsShortVectorType(Ins[i].ArgVT)); in AnalyzeFormalArguments()
74 ArgIsShortVector.push_back(IsShortVectorType(Outs[i].ArgVT)); in AnalyzeCallOperands()
H A DSystemZISelLowering.cpp1349 static void VerifyVectorType(MVT VT, EVT ArgVT) { in VerifyVectorType() argument
1350 if (ArgVT.isVector() && !VT.isVector()) in VerifyVectorType()
1356 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT); in VerifyVectorTypes()
1361 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT); in VerifyVectorTypes()
1733 SlotVT = Outs[I].ArgVT; in LowerCall()
1932 if (Out.ArgVT == MVT::i128) in CanLowerReturn()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetCallingConv.h198 EVT ArgVT; member
216 ArgVT = argvt; in InputArg()
236 EVT ArgVT; member
255 ArgVT = argvt; in OutputArg()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCCState.cpp19 if (I.ArgVT == llvm::MVT::ppcf128) in PreAnalyzeCallOperands()
29 if (I.ArgVT == llvm::MVT::ppcf128) { in PreAnalyzeFormalArguments()
H A DPPCFastISel.cpp1394 MVT ArgVT = ArgVTs[VA.getValNo()]; in processCallArgs() local
1398 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 || in processCallArgs()
1433 MVT ArgVT = ArgVTs[VA.getValNo()]; in processCallArgs() local
1448 ArgVT = DestVT; in processCallArgs()
1458 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true)) in processCallArgs()
1460 ArgVT = DestVT; in processCallArgs()
1473 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) { in processCallArgs()
1622 MVT ArgVT; in fastLowerCall() local
1623 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8) in fastLowerCall()
1629 if (ArgVT.isVector() || ArgVT == MVT::f128) in fastLowerCall()
[all …]
H A DPPCISelLowering.cpp3899 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotAlignment()
3900 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotAlignment()
3901 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotAlignment()
3902 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotAlignment()
3963 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) in CalculateStackSlotUsed()
3968 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotUsed()
3969 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotUsed()
3970 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotUsed()
3971 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotUsed()
5767 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, in LowerCall_32SVR4()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCCState.cpp125 originalEVTTypeIsVectorFloat(Out.ArgVT)); in PreAnalyzeReturnForVectorFloat()
129 void MipsCCState::PreAnalyzeReturnValue(EVT ArgVT) { in PreAnalyzeReturnValue() argument
130 OriginalRetWasFloatVector.push_back(originalEVTTypeIsVectorFloat(ArgVT)); in PreAnalyzeReturnValue()
H A DMipsFastISel.cpp1149 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs() local
1152 firstMVT = ArgVT; in processCallArgs()
1153 if (ArgVT == MVT::f32) { in processCallArgs()
1155 } else if (ArgVT == MVT::f64) { in processCallArgs()
1163 if (ArgVT == MVT::f32) { in processCallArgs()
1165 } else if (ArgVT == MVT::f64) { in processCallArgs()
1173 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) || in processCallArgs()
1174 (ArgVT == MVT::i8)) && in processCallArgs()
1204 MVT SrcVT = ArgVT; in processCallArgs()
1212 MVT SrcVT = ArgVT; in processCallArgs()
[all …]
H A DMipsCCState.h42 void PreAnalyzeReturnValue(EVT ArgVT);
H A DMipsISelLowering.cpp3345 unsigned ValSizeInBits = Outs[OutIdx].ArgVT.getSizeInBits(); in LowerCall()
3523 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); in LowerCallResult()
3565 EVT ArgVT, const SDLoc &DL, in UnpackFromArgumentSlot() argument
3577 unsigned ValSizeInBits = ArgVT.getSizeInBits(); in UnpackFromArgumentSlot()
3693 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); in LowerFormalArguments()
3744 UnpackFromArgumentSlot(ArgValue, VA, Ins[InsIdx].ArgVT, DL, DAG); in LowerFormalArguments()
3876 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); in LowerReturn()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1895 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64) in ProcessCallArgs()
1946 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) && in ProcessCallArgs()
1956 ArgVT = DestVT; in ProcessCallArgs()
1965 ArgVT = DestVT; in ProcessCallArgs()
1972 ArgVT = VA.getLocVT(); in ProcessCallArgs()
2236 MVT ArgVT; in ARMEmitLibcall() local
2244 ArgVTs.push_back(ArgVT); in ARMEmitLibcall()
2364 MVT ArgVT; in SelectCall() local
2365 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 && in SelectCall()
2366 ArgVT != MVT::i1) in SelectCall()
[all …]
H A DARMISelLowering.cpp2498 auto ArgVT = Outs[realArgIdx].ArgVT; in LowerCall() local
2499 if (isCmseNSCall && (ArgVT == MVT::f16)) { in LowerCall()
2501 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits()); in LowerCall()
3215 auto RetVT = Outs[realRVLocIdx].ArgVT; in LowerReturn()
9776 EVT ArgVT = Arg.getValueType(); in LowerFSINCOS() local
9777 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in LowerFSINCOS()
9831 DAG.getLoad(ArgVT, dl, CallResult.second, SRet, MachinePointerInfo()); in LowerFSINCOS()
9835 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl)); in LowerFSINCOS()
9839 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT); in LowerFSINCOS()
20403 EVT ArgVT = N->getOperand(i).getValueType(); in getDivRemArgList() local
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DVINTERPInstructions.td76 class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
H A DAMDGPUISelLowering.cpp965 EVT ArgVT = ValueVTs[Value]; in analyzeFormalArgumentsCompute() local
966 EVT MemVT = ArgVT; in analyzeFormalArgumentsCompute()
972 if (ArgVT.isExtended()) { in analyzeFormalArgumentsCompute()
977 MemVT = ArgVT; in analyzeFormalArgumentsCompute()
979 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
986 } else if (ArgVT.isVector() && in analyzeFormalArgumentsCompute()
987 ArgVT.getVectorNumElements() == NumRegs) { in analyzeFormalArgumentsCompute()
990 MemVT = ArgVT.getScalarType(); in analyzeFormalArgumentsCompute()
991 } else if (ArgVT.isExtended()) { in analyzeFormalArgumentsCompute()
995 unsigned MemoryBits = ArgVT.getStoreSizeInBits() / NumRegs; in analyzeFormalArgumentsCompute()
[all …]
H A DSIInstrInfo.td2382 field list<ValueType> ArgVT = _ArgVT;
2386 field ValueType DstVT = ArgVT[0];
2387 field ValueType Src0VT = ArgVT[1];
2388 field ValueType Src1VT = ArgVT[2];
2389 field ValueType Src2VT = ArgVT[3];
2558 class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
2568 class VOP_PAT_GEN <VOPProfile p, int mode=PatGenMode.NoPattern> : VOPProfile <p.ArgVT> {
H A DVOP3Instructions.td106 class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp3077 if (!ArgVT.isSimple()) return false; in fastLowerArguments()
3078 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
3302 MVT ArgVT = OutVTs[VA.getValNo()]; in fastLowerCall() local
3304 if (ArgVT == MVT::x86mmx) in fastLowerCall()
3316 if (ArgVT == MVT::i1) in fastLowerCall()
3322 ArgVT = VA.getLocVT(); in fastLowerCall()
3330 if (ArgVT == MVT::i1) { in fastLowerCall()
3333 ArgVT = MVT::i8; in fastLowerCall()
3342 ArgVT = VA.getLocVT(); in fastLowerCall()
3358 ArgVT = VA.getLocVT(); in fastLowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp853 MVT ArgVT = Ins[i].VT; in analyzeInputArgs() local
855 if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) { in analyzeInputArgs()
857 << EVT(ArgVT).getEVTString() << '\n'); in analyzeInputArgs()
867 MVT ArgVT = Outs[i].VT; in analyzeOutputArgs() local
869 if (Fn(i, ArgVT, CCValAssign::Full, CCInfo)) { in analyzeOutputArgs()
871 << EVT(ArgVT).getEVTString() << "\n"); in analyzeOutputArgs()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp498 MVT ArgVT = Args[ValNo].VT; in AnalyzeArguments() local
500 MVT LocVT = ArgVT; in AnalyzeArguments()
516 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, Align(2), ArgFlags); in AnalyzeArguments()
530 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); in AnalyzeArguments()
534 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); in AnalyzeArguments()
538 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); in AnalyzeArguments()
544 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); in AnalyzeArguments()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2911 EVT ArgVT = TLI.getValueType(DL, ArgTy); in fastLowerArguments() local
2912 if (!ArgVT.isSimple()) in fastLowerArguments()
2915 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments()
3010 MVT ArgVT = OutVTs[VA.getValNo()]; in processCallArgs() local
3022 MVT SrcVT = ArgVT; in processCallArgs()
3032 MVT SrcVT = ArgVT; in processCallArgs()
3058 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8; in processCallArgs()
3072 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment); in processCallArgs()
3074 if (!emitStore(ArgVT, ArgReg, Addr, MMO)) in processCallArgs()
H A DAArch64ISelLowering.cpp4077 EVT ArgVT = Arg.getValueType(); in LowerFSINCOS() local
4110 EVT ArgVT = Op.getOperand(0).getValueType(); in LowerBITCAST() local
4124 if (isTypeLegal(OpVT) && !isTypeLegal(ArgVT)) { in LowerBITCAST()
4139 if (ArgVT == MVT::f16 || ArgVT == MVT::bf16) in LowerBITCAST()
4142 assert(ArgVT == MVT::i16); in LowerBITCAST()
6247 MVT ArgVT = Outs[i].VT; in analyzeCallOperands() local
6267 ArgVT = MVT::i8; in analyzeCallOperands()
6269 ArgVT = MVT::i16; in analyzeCallOperands()
6273 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); in analyzeCallOperands()
6640 if (Outs[i].ArgVT == MVT::i1) { in LowerCall()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp4066 EVT ArgVT = N->op_begin()->getValueType(); in ExpandExtIntRes_DIVREM() local
4067 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() > 128 && in ExpandExtIntRes_DIVREM()
4069 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in ExpandExtIntRes_DIVREM()
4071 SDValue Output = DAG.CreateStackTemporary(ArgVT); in ExpandExtIntRes_DIVREM()
4079 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT); in ExpandExtIntRes_DIVREM()
4110 return DAG.getLoad(ArgVT, DL, Chain, Output, MachinePointerInfo()); in ExpandExtIntRes_DIVREM()
4462 EVT ArgVT = Op.getValueType(); in ExpandIntRes_XMULO() local
4463 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in ExpandIntRes_XMULO()
H A DLegalizeDAG.cpp2024 EVT ArgVT = Op.getValueType(); in ExpandLibCall() local
2025 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in ExpandLibCall()
2028 Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); in ExpandLibCall()
2029 Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned); in ExpandLibCall()
2182 EVT ArgVT = Op.getValueType(); in ExpandDivRemLibCall() local
2183 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); in ExpandDivRemLibCall()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10564 MVT ArgVT = ArgIdx.value().VT; in preAssignMask() local
10565 if (ArgVT.isVector() && ArgVT.getVectorElementType() == MVT::i1) in preAssignMask()
10583 MVT ArgVT = Ins[i].VT; in analyzeInputArgs() local
10593 if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, in analyzeInputArgs()
10597 << EVT(ArgVT).getEVTString() << '\n'); in analyzeInputArgs()
10614 MVT ArgVT = Outs[i].VT; in analyzeOutputArgs() local
10619 if (Fn(MF.getDataLayout(), ABI, i, ArgVT, ArgVT, CCValAssign::Full, in analyzeOutputArgs()
10623 << EVT(ArgVT).getEVTString() << "\n"); in analyzeOutputArgs()
11268 std::max(getPrefTypeAlign(Outs[i].ArgVT, DAG), in LowerCall()

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