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Searched refs:ArgRC (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp791 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
798 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
807 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
812 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs()
842 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
845 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
848 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
851 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
H A DAMDGPULegalizerInfo.h102 const TargetRegisterClass *ArgRC, LLT ArgTy) const;
H A DAMDGPULegalizerInfo.cpp3271 const TargetRegisterClass *ArgRC, in loadInputValue() argument
3278 *ArgRC, B.getDebugLoc(), ArgTy); in loadInputValue()
3307 const TargetRegisterClass *ArgRC; in loadInputValue() local
3309 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in loadInputValue()
3327 return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy); in loadInputValue()
3356 const TargetRegisterClass *ArgRC; in legalizeWorkitemIDIntrinsic() local
3358 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in legalizeWorkitemIDIntrinsic()
H A DSIISelLowering.cpp2795 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
2804 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
2814 assert(IncomingArgRC == ArgRC); in passSpecialInputs()
2817 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32; in passSpecialInputs()
2821 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs()
2855 const TargetRegisterClass *ArgRC; in passSpecialInputs() local
2858 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
2861 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
2864 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs()
2895 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY); in passSpecialInputs()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp17173 const TargetRegisterClass *ArgRC = in canMergeExpensiveCrossRegisterBankCopy() local
17176 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy()
17184 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()