Searched refs:And0 (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1627 Instruction *And0 = dyn_cast<Instruction>(I->getOperand(0)); in setupPreSimplifier() local
1629 if (!And0 || !And1) in setupPreSimplifier()
1631 if (And0->getOpcode() != Instruction::And || in setupPreSimplifier()
1634 if (And0->getOperand(1) != And1->getOperand(1)) in setupPreSimplifier()
1637 return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)), in setupPreSimplifier()
1638 And0->getOperand(1)); in setupPreSimplifier()
1759 Instruction *And0 = dyn_cast<Instruction>(Xor->getOperand(0)); in setupPostSimplifier() local
1762 if (!And0 || And0->getOpcode() != Instruction::And) in setupPostSimplifier()
1763 std::swap(And0, And1); in setupPostSimplifier()
1764 ConstantInt *C1 = dyn_cast<ConstantInt>(And0->getOperand(1)); in setupPostSimplifier()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 2767 SDValue And0 = N->getOperand(0); in tryBitfieldInsertOpFromOr() local
2769 if (And0.hasOneUse() && And1.hasOneUse() && in tryBitfieldInsertOpFromOr()
2770 isOpcWithIntImmediate(And0.getNode(), ISD::AND, Mask0Imm) && in tryBitfieldInsertOpFromOr()
2779 std::swap(And0, And1); in tryBitfieldInsertOpFromOr()
2784 SDValue Dst = And0->getOperand(0); in tryBitfieldInsertOpFromOr()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 857 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); in performORCombine() local
862 if (And0.getOpcode() != ISD::AND) in performORCombine()
865 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || in performORCombine()
898 And0.getOperand(0)); in performORCombine()
938 And0->getOperand(0)); in performORCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4437 SDValue And0 = And->getOperand(0); in shrinkAndImmediate() local
4455 if (!CurDAG->MaskedValueIsZero(And0, HighZeros)) in shrinkAndImmediate()
4461 ReplaceNode(And, And0.getNode()); in shrinkAndImmediate()
4468 SDValue NewAnd = CurDAG->getNode(ISD::AND, SDLoc(And), VT, And0, NewMask); in shrinkAndImmediate()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 5999 SDValue And0 = And->getOperand(0), And1 = And->getOperand(1); in combineShiftAnd1ToBitTest() local
6000 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
6001 And0 = And0.getOperand(0); in combineShiftAnd1ToBitTest()
6002 if (!isOneConstant(And1) || !And0.hasOneUse()) in combineShiftAnd1ToBitTest()
6005 SDValue Src = And0; in combineShiftAnd1ToBitTest()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6353 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); in lowerFCopySign() local
6373 MIRBuilder.buildOr(Dst, And0, And1, Flags); in lowerFCopySign()
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