Home
last modified time | relevance | path

Searched refs:AllocateReg (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h121 Reg = State.AllocateReg(SystemZ::ELFArgGPRs); in CC_SystemZ_I128Indirect()
123 Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_SystemZ_I128Indirect()
149 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
153 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
154 State.AllocateReg(SystemZ::XPLINK64ArgGPRs); in CC_XPLINK64_Shadow_Reg()
161 State.AllocateReg(SystemZ::XPLINK64ArgFPRs[I + 1]); in CC_XPLINK64_Shadow_Reg()
178 State.AllocateReg(SystemZ::R1D); in CC_XPLINK64_Allocate128BitVararg()
180 bool AllocGPR2 = State.AllocateReg(SystemZ::R2D); in CC_XPLINK64_Allocate128BitVararg()
181 bool AllocGPR3 = State.AllocateReg(SystemZ::R3D); in CC_XPLINK64_Allocate128BitVararg()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.h30 Register Reg = State.AllocateReg(ArgGPRs); in CC_CSKY_ABIV2_SOFT_64()
38 if (!State.AllocateReg(ArgGPRs)) in CC_CSKY_ABIV2_SOFT_64()
49 Register Reg = State.AllocateReg(ArgGPRs); in Ret_CSKY_ABIV2_SOFT_64()
54 if (!State.AllocateReg(ArgGPRs)) in Ret_CSKY_ABIV2_SOFT_64()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.cpp49 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
74 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
98 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
118 unsigned Reg = State.AllocateReg(HiRegList); in CC_PPC32_SPE_CustomSplitFP64()
127 unsigned T = State.AllocateReg(LoRegList[i]); in CC_PPC32_SPE_CustomSplitFP64()
147 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in CC_PPC32_SPE_RetF64()
H A DPPCISelLowering.cpp6630 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6657 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6672 unsigned FReg = State.AllocateReg(FPR); in CC_AIX()
6678 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
6718 if (unsigned VReg = State.AllocateReg(VR)) { in CC_AIX()
6739 unsigned Reg = State.AllocateReg(GPRs); in CC_AIX()
6751 if (unsigned VReg = State.AllocateReg(VR)) { in CC_AIX()
6755 State.AllocateReg(GPRs); in CC_AIX()
6780 const unsigned FirstReg = State.AllocateReg(PPC::R9); in CC_AIX()
6781 const unsigned SecondReg = State.AllocateReg(PPC::R10); in CC_AIX()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.cpp27 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
41 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
70 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS()
74 Reg = State.AllocateReg(GPRArgRegs); in f64AssignAAPCS()
92 unsigned T = State.AllocateReg(LoRegList[i]); in f64AssignAAPCS()
119 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
265 State.AllocateReg(Reg); in CC_ARM_AAPCS_Custom_Aggregate()
290 unsigned Reg = State.AllocateReg(RegList); in CustomAssignInRegList()
H A DARMISelLowering.cpp2863 unsigned Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2870 Reg = State->AllocateReg(GPRArgRegs); in HandleByVal()
2883 while (State->AllocateReg(GPRArgRegs)) in HandleByVal()
2900 State->AllocateReg(GPRArgRegs); in HandleByVal()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.cpp53 unsigned Reg = State.AllocateReg(AvailableRegs[I]); in CC_X86_32_RegCall_Assign2Regs()
104 unsigned AssigedReg = State.AllocateReg(Reg); in CC_X86_VectorCallAssignRegister()
149 (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT)); in CC_X86_64_VectorCall()
157 (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs()); in CC_X86_64_VectorCall()
160 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_64_VectorCall()
211 if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) { in CC_X86_32_VectorCall()
261 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
282 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kCallingConv.h65 IsPtr ? State.AllocateReg(AddrRegList) : State.AllocateReg(DataRegList); in CC_M68k_Any_AssignToReg()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp448 CCInfo.AllocateReg(PrivateSegmentBufferReg); in allocateHSAUserSGPRs()
454 CCInfo.AllocateReg(DispatchPtrReg); in allocateHSAUserSGPRs()
460 CCInfo.AllocateReg(QueuePtrReg); in allocateHSAUserSGPRs()
471 CCInfo.AllocateReg(InputPtrReg); in allocateHSAUserSGPRs()
477 CCInfo.AllocateReg(DispatchIDReg); in allocateHSAUserSGPRs()
483 CCInfo.AllocateReg(FlatScratchInitReg); in allocateHSAUserSGPRs()
593 CCInfo.AllocateReg(ImplicitBufferPtrReg); in lowerFormalArguments()
600 CCInfo.AllocateReg(FlatScratchInitReg); in lowerFormalArguments()
673 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
674 CCInfo.AllocateReg(AMDGPU::VGPR1); in lowerFormalArguments()
[all …]
H A DSIISelLowering.cpp1888 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1903 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1917 CCInfo.AllocateReg(Reg); in allocateSpecialEntryInputVGPRs()
1943 Reg = CCInfo.AllocateReg(Reg); in allocateVGPR32Input()
1961 Reg = CCInfo.AllocateReg(Reg); in allocateSGPR32InputImpl()
2124 CCInfo.AllocateReg(Reg); in allocateHSAUserSGPRs()
2152 CCInfo.AllocateReg(Reg); in allocateSystemSGPRs()
2159 CCInfo.AllocateReg(Reg); in allocateSystemSGPRs()
2165 CCInfo.AllocateReg(Reg); in allocateSystemSGPRs()
2171 CCInfo.AllocateReg(Reg); in allocateSystemSGPRs()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h349 MCRegister AllocateReg(MCPhysReg Reg) { in AllocateReg() function
357 MCRegister AllocateReg(MCPhysReg Reg, MCPhysReg ShadowReg) { in AllocateReg() function
368 MCPhysReg AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() function
409 MCRegister AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg() function
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp65 State.AllocateReg(ZRegList[I]); in finishStackBlock()
192 State.AllocateReg(Reg); in CC_AArch64_Custom_Block()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2926 State.AllocateReg(Mips::A1); in CC_MipsO32()
2928 State.AllocateReg(Mips::A3); in CC_MipsO32()
2932 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2936 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2940 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2947 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2949 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2963 Reg = State.AllocateReg(F32Regs); in CC_MipsO32()
2965 State.AllocateReg(IntRegs); in CC_MipsO32()
2971 State.AllocateReg(IntRegs); in CC_MipsO32()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp835 Reg = State.AllocateReg(ArgFPR32s); in CC_LoongArch()
837 Reg = State.AllocateReg(ArgFPR64s); in CC_LoongArch()
839 Reg = State.AllocateReg(ArgGPRs); in CC_LoongArch()
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp1131 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeArguments()
1133 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeArguments()
1197 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeReturnValues()
1199 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeReturnValues()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp10332 return State.AllocateReg(RISCV::V0); in allocateRVVReg()
10333 return State.AllocateReg(ArgVRs); in allocateRVVReg()
10336 return State.AllocateReg(ArgVRM2s); in allocateRVVReg()
10338 return State.AllocateReg(ArgVRM4s); in allocateRVVReg()
10340 return State.AllocateReg(ArgVRM8s); in allocateRVVReg()
10414 State.AllocateReg(ArgGPRs); in CC_RISCV()
10441 if (!State.AllocateReg(ArgGPRs)) in CC_RISCV()
10487 Reg = State.AllocateReg(ArgFPR16s); in CC_RISCV()
10489 Reg = State.AllocateReg(ArgFPR32s); in CC_RISCV()
10491 Reg = State.AllocateReg(ArgFPR64s); in CC_RISCV()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp529 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
537 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp62 if (Register Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
72 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
89 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
95 if (Register Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp152 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()