| /llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 120 AddSub, enumerator
268 return FirstMacroFusionInstKind::AddSub; in classifyFirstOpcodeInMacroFusion()
345 case X86::FirstMacroFusionInstKind::AddSub: in isMacroFused()
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| /llvm-project-15.0.7/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 878 BinaryOperator *AddSub; in matchSAddSubSat() local
881 if (!match(MinMax2, m_SMax(m_BinOp(AddSub), m_APInt(MinValue)))) in matchSAddSubSat()
885 if (!match(MinMax2, m_SMin(m_BinOp(AddSub), m_APInt(MaxValue)))) in matchSAddSubSat()
902 if (!MinMax2->hasOneUse() || !AddSub->hasOneUse()) in matchSAddSubSat()
909 if (AddSub->getOpcode() == Instruction::Add) in matchSAddSubSat()
911 else if (AddSub->getOpcode() == Instruction::Sub) in matchSAddSubSat()
918 if (ComputeMaxSignificantBits(AddSub->getOperand(0), 0, AddSub) > in matchSAddSubSat()
920 ComputeMaxSignificantBits(AddSub->getOperand(1), 0, AddSub) > NewBitWidth) in matchSAddSubSat()
925 Value *AT = Builder.CreateTrunc(AddSub->getOperand(0), NewTy); in matchSAddSubSat()
926 Value *BT = Builder.CreateTrunc(AddSub->getOperand(1), NewTy); in matchSAddSubSat()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 722 ARM_AM::AddrOpc AddSub = ARM_AM::add; in SelectLdStSOReg() local
724 AddSub = ARM_AM::sub; in SelectLdStSOReg()
827 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg() local
863 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre() local
867 if (AddSub == ARM_AM::sub) Val *= -1; in SelectAddrMode2OffsetImmPre()
883 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm() local
888 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, in SelectAddrMode2OffsetImm()
939 ARM_AM::AddrOpc AddSub = ARM_AM::add; in SelectAddrMode3() local
941 AddSub = ARM_AM::sub; in SelectAddrMode3()
1009 ARM_AM::AddrOpc AddSub = ARM_AM::add; in IsAddressingMode5() local
[all …]
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| H A D | ARMLoadStoreOptimizer.cpp | 1521 ARM_AM::AddrOpc AddSub = Offset < 0 ? ARM_AM::sub : ARM_AM::add; in MergeBaseUpdateLoadStore() local
1555 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1585 int Imm = ARM_AM::getAM2Opc(AddSub, abs(Offset), ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
2307 ARM_AM::AddrOpc AddSub = ARM_AM::add; in CanFormLdStDWord() local
2309 AddSub = ARM_AM::sub; in CanFormLdStDWord()
2315 Offset = ARM_AM::getAM3Opc(AddSub, OffImm); in CanFormLdStDWord()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2961 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode2Operands() local
2967 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2986 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM2OffsetImmOperands() local
2990 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
3020 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAddrMode3Operands()
3046 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAM3OffsetOperands() local
3050 Val = ARM_AM::getAM3Opc(AddSub, Val); in addAM3OffsetOperands()
3072 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode5Operands() local
3078 Val = ARM_AM::getAM5Opc(AddSub, Val); in addAddrMode5Operands()
3101 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; in addAddrMode5FP16Operands() local
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | SVEInstrFormats.td | 172 def SVEAddSubImmOperand8 : SVEShiftedImmOperand<8, "AddSub", "isSVEAddSubImm<int8_t>">;
173 def SVEAddSubImmOperand16 : SVEShiftedImmOperand<16, "AddSub", "isSVEAddSubImm<int16_t>">;
174 def SVEAddSubImmOperand32 : SVEShiftedImmOperand<32, "AddSub", "isSVEAddSubImm<int32_t>">;
175 def SVEAddSubImmOperand64 : SVEShiftedImmOperand<64, "AddSub", "isSVEAddSubImm<int64_t>">;
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| H A D | AArch64InstrInfo.td | 1679 defm ADD : AddSub<0, "add", "sub", add>;
1680 defm SUB : AddSub<1, "sub", "add">;
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| H A D | AArch64InstrFormats.td | 2567 multiclass AddSub<bit isSub, string mnemonic, string alias,
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 11109 if (SDValue AddSub = lowerToAddSubOrFMAddSub(BV, Subtarget, DAG)) in LowerBUILD_VECTOR() local
11110 return AddSub; in LowerBUILD_VECTOR()
40787 if (SDValue AddSub = combineShuffleToAddSubOrFMAddSub(N, Subtarget, DAG)) in combineShuffle() local
40788 return AddSub; in combineShuffle()
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