| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VVPISelLowering.cpp | 24 SDValue AVL = in splitMaskArithmetic() local
63 SDValue AVL; in lowerToVVP() local
77 if (!AVL) in lowerToVVP()
132 SDValue AVL = getNodeAVL(Op); in lowerVVP_LOAD_STORE() local
144 if (!AVL) in lowerVVP_LOAD_STORE()
208 UpperPartAVL = SplitTM.AVL; in splitPackedLoadStore()
232 OpVec.push_back(SplitTM.AVL); in splitPackedLoadStore()
284 if (!AVL) in lowerVVP_GATHER_SCATTER()
404 auto AVL = getNodeAVL(Op); in legalizePackedAVL() local
405 if (isLegalAVL(AVL)) in legalizePackedAVL()
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| H A D | VECustomDAG.cpp | 214 bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; } in isLegalAVL() argument
396 SDValue AVL = getNodeAVL(Op); in getAnnotatedNodeAVL() local
397 if (!AVL) in getAnnotatedNodeAVL()
399 if (isLegalAVL(AVL)) in getAnnotatedNodeAVL()
400 return {AVL->getOperand(0), true}; in getAnnotatedNodeAVL()
401 return {AVL, false}; in getAnnotatedNodeAVL()
475 if (isLegalAVL(AVL)) in annotateLegalAVL()
476 return AVL; in annotateLegalAVL()
477 return getNode(VEISD::LEGALAVL, AVL.getValueType(), AVL); in annotateLegalAVL()
487 return DAG.getNode(OC, DL, DestVT, Vec, AVL); in getUnpack()
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| H A D | VECustomDAG.h | 77 bool isLegalAVL(SDValue AVL);
137 SDValue AVL; member
138 VETargetMasks(SDValue Mask = SDValue(), SDValue AVL = SDValue())
139 : Mask(Mask), AVL(AVL) {} in Mask()
185 SDValue VectorV, SDValue Mask, SDValue AVL,
190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
202 SDValue getMaskBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
203 SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
206 SDValue annotateLegalAVL(SDValue AVL) const;
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| H A D | VEISelLowering.cpp | 1834 auto AVL = CDAG.getConstant(NumEls, MVT::i32); in lowerBUILD_VECTOR() local
1835 return CDAG.getBroadcast(ResultVT, ScalarV, AVL); in lowerBUILD_VECTOR()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVSDPatterns.td | 69 (load_instr GPR:$rs1, m.AVL, m.Log2SEW)>;
170 fvti.AVL, fvti.Log2SEW)>;
244 vti.AVL, vti.Log2SEW)>;
262 fvti.AVL, fvti.Log2SEW)>;
268 fvti.AVL, fvti.Log2SEW)>;
390 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC
404 vti.AVL, vti.Log2SEW, TAIL_AGNOSTIC
771 vti.AVL, vti.Log2SEW)>;
974 fvti.AVL, fvti.Log2SEW)>;
1026 fvti.AVL, fvti.Log2SEW)>;
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| H A D | RISCVInstrInfoVPseudos.td | 25 def AVL : RegisterOperand<GPRNoX0> {
31 // rd | rs1 | AVL value | Effect on vl
193 OutPatFrag AVL = VLMax;
303 OutPatFrag AVL = VLMax;
648 (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
787 (ins GPR:$rs1, IdxClass:$rs2, AVL:$vl,
915 (ins AVL:$vl, ixlenimm:$sew),
1047 VR:$vm, AVL:$vl, ixlenimm:$sew),
1272 AVL:$vl, ixlenimm:$sew),
1307 (ins GPR:$rs1, AVL:$vl, ixlenimm:$sew),[]>,
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| H A D | RISCVInsertVSETVLI.cpp | 1275 unsigned AVL = Info.getAVLImm(); in hasFixedResult() local
1277 unsigned AVLInBits = AVL * SEW; in hasFixedResult()
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| H A D | RISCVISelDAGToDAG.cpp | 562 uint64_t AVL = C->getZExtValue(); in selectVSETVLI() local
563 if (isUInt<5>(AVL)) { in selectVSETVLI()
564 SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT); in selectVSETVLI()
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| H A D | RISCVISelLowering.cpp | 4732 SDValue AVL = getVLOperand(Op); in lowerVectorIntrinsicScalars() local
4736 if (isa<ConstantSDNode>(AVL)) { in lowerVectorIntrinsicScalars()
4748 uint64_t AVLInt = cast<ConstantSDNode>(AVL)->getZExtValue(); in lowerVectorIntrinsicScalars()
4776 SDValue VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVL, AVL, in lowerVectorIntrinsicScalars()
4822 AVL); in lowerVectorIntrinsicScalars()
4826 AVL); in lowerVectorIntrinsicScalars()
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/ |
| H A D | vsetvli-insert-crossbb.ll | 498 ; VTYPEs. The AVL is the same and the SEW/LMUL ratio implies the same VLMAX so
499 ; we don't need to read AVL and can keep VL unchanged.
671 ; Same as above, but VL comes from user provided AVL value
778 ; Same as above, but AVL is only specified on the store intrinsic
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| H A D | vsetvli-insert.ll | 543 ; Ensure AVL register is alive when forwarding an AVL immediate that does not fit in 5 bits
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| H A D | vadd-vp.ll | 1644 ; FIXME: The first vadd.vi should be able to infer that its AVL is equivalent to VLMAX.
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsRISCV.td | 160 /* AVL */ [LLVMMatchType<0>,
176 /* AVL */ [LLVMMatchType<0>,
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| /llvm-project-15.0.7/llvm/docs/ |
| H A D | ProgrammersManual.rst | 2176 ImmutableSet is an immutable (functional) set implementation based on an AVL
2369 ImmutableMap is an immutable (functional) map implementation based on an AVL
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