| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCV.td | 265 "'Zknd' (NIST Suite: AES Decryption)">;
268 "'Zknd' (NIST Suite: AES Decryption)">;
272 "'Zkne' (NIST Suite: AES Encryption)">;
275 "'Zkne' (NIST Suite: AES Encryption)">;
282 "'Zknd' (NIST Suite: AES Decryption) or "
283 "'Zkne' (NIST Suite: AES Encryption)">;
|
| /llvm-project-15.0.7/clang/lib/Basic/Targets/ |
| H A D | ARM.cpp | 485 AES = 0; in handleTargetFeatures()
542 AES = 1; in handleTargetFeatures()
714 if (SHA2 && AES) in getTargetDefines()
718 if (AES) in getTargetDefines()
|
| H A D | ARM.h | 77 unsigned AES : 1; variable
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ARM/ |
| H A D | aes-intrinsics.ll | 2 ; ARM AES intrinsic variants
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/ |
| H A D | aes-intrinsics.ll | 2 ; ARM64 AES intrinsic variants
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64.td | 42 "Enable AES support", [FeatureNEON]>;
50 // compatibility, and now imply features SHA2 and AES, which was the
144 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
247 "CPU fuses AES crypto operations">;
259 "CPU fuses AES/PMULL and EOR operations">;
764 // Note that cyclone does not fuse AES instructions, but newer apple chips do
|
| H A D | AArch64SchedAmpere1.td | 698 // -- AES encryption/decryption
699 def : InstRW<[Ampere1Write_2cyc_1XY], (instregex "^AES[DE]")>;
|
| H A D | AArch64SchedNeoverseN2.td | 1440 // Crypto AES ops
1441 def : InstRW<[N2Write_2cyc_1V], (instregex "^AES[DE]rr$", "^AESI?MCrr")>;
2267 // Crypto AES ops
2268 def : InstRW<[N2Write_2cyc_1V], (instregex "^AES[DE]_ZZZ_B$",
|
| H A D | AArch64SchedTSV110.td | 350 def : InstRW<[TSV110Wr_3cyc_1FSU1], (instregex "^AES[DE]")>;
|
| H A D | AArch64SchedExynosM3.td | 865 def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>;
|
| H A D | AArch64SchedA57.td | 172 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES[DE]")>;
|
| H A D | AArch64SchedExynosM4.td | 1004 def : InstRW<[M4WriteNCRY1], (instregex "^AES[DE]")>;
|
| H A D | AArch64SchedExynosM5.td | 1001 def : InstRW<[M5WriteNCRY2], (instregex "^AES[DE]")>;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARM.td | 192 "Enable AES support", [FeatureNEON]>;
221 // Fast execution of AES crypto operations.
222 // True if processor executes back to back AES instruction pairs faster.
224 "CPU fuses AES crypto operations">;
547 "Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)">;
|
| H A D | ARMScheduleA57.td | 1464 // Crypto AES ops
1466 def : InstRW<[A57Write_3cyc_1W], (instregex "^AES")>;
|
| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | O3-pipeline.ll | 193 ; CHECK-NEXT: ARM fix for Cortex-A57 AES Erratum 1742098
|
| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | X86TargetParser.def | 127 X86_FEATURE_COMPAT(AES, "aes", 10)
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleSLM.td | 450 // AES Instructions.
|
| H A D | X86ScheduleZnver3.td | 258 // *AES*
324 // *AES*
1300 // AES instructions.
|
| H A D | X86.td | 203 "Enable AES instructions",
206 "Promote selected AES instructions to AVX512/AVX registers",
|
| H A D | X86ScheduleAtom.td | 472 // AES instructions.
|
| H A D | X86Schedule.td | 477 // AES instructions.
|
| H A D | X86ScheduleBtVer2.td | 773 // AES Instructions.
|
| H A D | X86ScheduleBdVer2.td | 1253 // AES Instructions.
|
| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | IntrinsicsAArch64.td | 783 // AES
2497 // SVE2 - Optional AES, SHA-3 and SM4
|