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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1 |
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| #
650aec68 |
| 03-Feb-2022 |
tyb0807 <[email protected]> |
[ARM][AArch64] Add missing v8.x checks
Summary: This patch adds checks that were missing in clang for Armv8.5/6/7-A. These include: * ACLE macro defines for AArch32. * Handling of crypto and SM4, SH
[ARM][AArch64] Add missing v8.x checks
Summary: This patch adds checks that were missing in clang for Armv8.5/6/7-A. These include: * ACLE macro defines for AArch32. * Handling of crypto and SM4, SHA and AES feature flags on clang's driver.
Reviewers: dmgreen, SjoerdMeijer, tmatheson
Differential Revision: https://reviews.llvm.org/D116153
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Revision tags: llvmorg-15-init |
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1f08b086 |
| 28-Jan-2022 |
Amilendra Kodithuwakku <[email protected]> |
[clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures
Branch protection in M-class is supported by - Armv8.1-M.Main - Armv8-M.Main - Armv7-M
Attempting to enable this f
[clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures
Branch protection in M-class is supported by - Armv8.1-M.Main - Armv8-M.Main - Armv7-M
Attempting to enable this for other architectures, either by command-line (e.g -mbranch-protection=bti) or by target attribute in source code (e.g. __attribute__((target("branch-protection=..."))) ) will generate a warning.
In both cases function attributes related to branch protection will not be emitted. Regardless of the warning, module level attributes related to branch protection will be emitted when it is enabled via the command-line.
The following people also contributed to this patch: - Victor Campos
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D115501
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Revision tags: llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2 |
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4435d181 |
| 21-Dec-2021 |
Tomas Matheson <[email protected]> |
[ARM][AArch64] clang support for Armv9.3-A
This patch introduces support for targetting the Armv9.3-A architecture, which should map to the existing Armv8.8-A extensions.
Differential Revision: htt
[ARM][AArch64] clang support for Armv9.3-A
This patch introduces support for targetting the Armv9.3-A architecture, which should map to the existing Armv8.8-A extensions.
Differential Revision: https://reviews.llvm.org/D116159
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Revision tags: llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2 |
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| #
d50072f7 |
| 11-Feb-2021 |
Simon Tatham <[email protected]> |
[ARM] Introduce an empty "armv8.8-a" architecture.
This is the first commit in a series that implements support for "armv8.8-a" architecture. This should contain all the necessary boilerplate to mak
[ARM] Introduce an empty "armv8.8-a" architecture.
This is the first commit in a series that implements support for "armv8.8-a" architecture. This should contain all the necessary boilerplate to make the 8.8-A architecture exist from LLVM and Clang's point of view: it adds the new arch as a subtarget feature, a definition in TargetParser, a name on the command line, an appropriate set of predefined macros, and adds appropriate tests. The new architecture name is supported in both AArch32 and AArch64.
However, in this commit, no actual _functionality_ is added as part of the new architecture. If you specify -march=armv8.8a, the compiler will accept it and set the right predefines, but generate no code any differently.
Differential Revision: https://reviews.llvm.org/D115694
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bfe07195 |
| 09-Dec-2021 |
Ties Stuij <[email protected]> |
[ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT
When using -mbranch-protection=pac-ret+b-key, macro __ARM_FEATURE_PAC_DEFAULT should still have the value corresponding to a-key,
[ARM][clang] Option b-key must not affect __ARM_FEATURE_PAC_DEFAULT
When using -mbranch-protection=pac-ret+b-key, macro __ARM_FEATURE_PAC_DEFAULT should still have the value corresponding to a-key, because b-key is only valid for AArch64.
This patch is part of a series that adds support for the PACBTI-M extension of the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Victor Campos
Reviewed By: danielkiss
Differential Revision: https://reviews.llvm.org/D115140
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e32b818d |
| 09-Dec-2021 |
Ties Stuij <[email protected]> |
[ARM][clang] Define feature test macro for the PACBTI-M extension
If the extension string "+pacbti" was given in -march=... or -mcpu=... options the compiler shall define the following preprocessor
[ARM][clang] Define feature test macro for the PACBTI-M extension
If the extension string "+pacbti" was given in -march=... or -mcpu=... options the compiler shall define the following preprocessor macros:
__ARM_FEATURE_PAUTH with value 1. __ARM_FEATURE_BTI with value 1.
This patch is part of a series that adds support for the PACBTI-M extension of the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov - Ties Stuij
Reviewed By: miyuki
Differential Revision: https://reviews.llvm.org/D112431
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| #
ab2611d0 |
| 01-Dec-2021 |
Ties Stuij <[email protected]> |
[clang][ARM] emit PACBTI-M feature defines
emit __ARM_FEATURE_BTI_DEFAULT and __ARM_FEATURE_PAC_DEFAULT defines when those features have been enabled
This patch is part of a series that adds suppor
[clang][ARM] emit PACBTI-M feature defines
emit __ARM_FEATURE_BTI_DEFAULT and __ARM_FEATURE_PAC_DEFAULT defines when those features have been enabled
This patch is part of a series that adds support for the PACBTI-M extension of the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Victor Campos - Ties Stuij
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D112422
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e3b2f022 |
| 01-Dec-2021 |
Ties Stuij <[email protected]> |
[clang][ARM] PACBTI-M frontend support
Handle branch protection option on the commandline as well as a function attribute. One patch for both mechanisms, as they use the same underlying parsing mech
[clang][ARM] PACBTI-M frontend support
Handle branch protection option on the commandline as well as a function attribute. One patch for both mechanisms, as they use the same underlying parsing mechanism.
These are recorded in a set of LLVM IR module-level attributes like we do for AArch64 PAC/BTI (see https://reviews.llvm.org/D85649):
- command-line options are "translated" to module-level LLVM IR attributes (metadata).
- functions have PAC/BTI specific attributes iff the __attribute__((target("branch-protection=...))) was used in the function declaration.
- command-line option -mbranch-protection to armclang targeting Arm, following this grammar:
branch-protection ::= "-mbranch-protection=" <protection> protection ::= "none" | "standard" | "bti" [ "+" <pac-ret-clause> ] | <pac-ret-clause> [ "+" "bti"] pac-ret-clause ::= "pac-ret" [ "+" <pac-ret-option> ] pac-ret-option ::= "leaf" ["+" "b-key"] | "b-key" ["+" "leaf"]
b-key is simply a placeholder to make it consistent with AArch64's version. In Arm, however, it triggers a warning informing that b-key is unsupported and a-key will be selected instead.
- Handle _attribute_((target(("branch-protection=..."))) for AArch32 with the same grammer as the commandline options.
This patch is part of a series that adds support for the PACBTI-M extension of the Armv8.1-M architecture, as detailed here:
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension
The PACBTI-M specification can be found in the Armv8-M Architecture Reference Manual:
https://developer.arm.com/documentation/ddi0553/latest
The following people contributed to this patch:
- Momchil Velikov - Victor Campos - Ties Stuij
Reviewed By: vhscampos
Differential Revision: https://reviews.llvm.org/D112421
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cb9a0dc2 |
| 20-Oct-2021 |
Pavel Kosov <[email protected]> |
[ARM] Fix inline assembly referencing floating point registers on soft-float targets
Fixes PR: https://bugs.llvm.org/show_bug.cgi?id=52230
Reviewed By: nickdesaulniers
Differential Revision: https
[ARM] Fix inline assembly referencing floating point registers on soft-float targets
Fixes PR: https://bugs.llvm.org/show_bug.cgi?id=52230
Reviewed By: nickdesaulniers
Differential Revision: https://reviews.llvm.org/D112135
OS Laboratory, Huawei Russian Research Institute, Saint-Petersburg
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3550e242 |
| 08-Sep-2021 |
Victor Campos <[email protected]> |
[Clang][ARM][AArch64] Add support for Armv9-A, Armv9.1-A and Armv9.2-A
armv9-a, armv9.1-a and armv9.2-a can be targeted using the -march option both in ARM and AArch64.
- Armv9-A maps to Armv8.5-A
[Clang][ARM][AArch64] Add support for Armv9-A, Armv9.1-A and Armv9.2-A
armv9-a, armv9.1-a and armv9.2-a can be targeted using the -march option both in ARM and AArch64.
- Armv9-A maps to Armv8.5-A. - Armv9.1-A maps to Armv8.6-A. - Armv9.2-A maps to Armv8.7-A. - The SVE2 extension is enabled by default on these architectures. - The cryptographic extensions are disabled by default on these architectures.
The Armv9-A architecture is described in the Arm® Architecture Reference Manual Supplement Armv9, for Armv9-A architecture profile (https://developer.arm.com/documentation/ddi0608/latest).
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D109517
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92dcb1d2 |
| 22-Jun-2021 |
Varun Gandhi <[email protected]> |
[Clang] Introduce Swift async calling convention.
This change is intended as initial setup. The plan is to add more semantic checks later. I plan to update the documentation as more semantic checks
[Clang] Introduce Swift async calling convention.
This change is intended as initial setup. The plan is to add more semantic checks later. I plan to update the documentation as more semantic checks are added (instead of documenting the details up front). Most of the code closely mirrors that for the Swift calling convention. Three places are marked as [FIXME: swiftasynccc]; those will be addressed once the corresponding convention is introduced in LLVM.
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D95561
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3d59f9d2 |
| 14-May-2021 |
David Candler <[email protected]> |
[ARM][AArch64] Correct __ARM_FEATURE_CRYPTO macro and crypto feature
This patch contains a couple of minor corrections to my previous crypto patch:
Since both AArch32 and AArch64 are now correctly
[ARM][AArch64] Correct __ARM_FEATURE_CRYPTO macro and crypto feature
This patch contains a couple of minor corrections to my previous crypto patch:
Since both AArch32 and AArch64 are now correctly setting the aes and sha2 features individually, it is not necessary to continue to check the crypto feature when defining feature macros.
In the AArch32 driver, the feature vector is only modified when the crypto feature is actually in the vector. If crypto is not present, there is no need to split it and explicitly define crypto/sha2/aes.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D102406
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b8baa2a9 |
| 28-Apr-2021 |
David Candler <[email protected]> |
[ARM][AArch64] Require appropriate features for crypto algorithms
This patch changes the AArch32 crypto instructions (sha2 and aes) to require the specific sha2 or aes features. These features have
[ARM][AArch64] Require appropriate features for crypto algorithms
This patch changes the AArch32 crypto instructions (sha2 and aes) to require the specific sha2 or aes features. These features have already been implemented and can be controlled through the command line, but do not have the expected result (i.e. `+noaes` will not disable aes instructions). The crypto feature retains its existing meaning of both sha2 and aes.
Several small changes are included due to the knock-on effect this has:
- The AArch32 driver has been modified to ensure sha2/aes is correctly set based on arch/cpu/fpu selection and feature ordering. - Crypto extensions are permitted for AArch32 v8-R profile, but not enabled by default. - ACLE feature macros have been updated with the fine grained crypto algorithms. These are also used by AArch64. - Various tests updated due to the change in feature lists and macros.
Reviewed By: lenary
Differential Revision: https://reviews.llvm.org/D99079
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0f1137ba |
| 19-Apr-2021 |
Nico Weber <[email protected]> |
[clang/Basic] Make TargetInfo.h not use DataLayout again
Reverts parts of https://reviews.llvm.org/D17183, but keeps the resetDataLayout() API and adds an assert that checks that datalayout string a
[clang/Basic] Make TargetInfo.h not use DataLayout again
Reverts parts of https://reviews.llvm.org/D17183, but keeps the resetDataLayout() API and adds an assert that checks that datalayout string and user label prefix are in sync.
Approach 1 in https://reviews.llvm.org/D17183#2653279 Reduces number of TUs build for 'clang-format' from 689 to 575.
I also implemented approach 2 in D100764. If someone feels motivated to make us use DataLayout more, it's easy to revert this change here and go with D100764 instead. I don't plan on doing more work in this area though, so I prefer going with the smaller, more self-consistent change.
Differential Revision: https://reviews.llvm.org/D100776
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ee3e0162 |
| 12-Apr-2021 |
Victor Campos <[email protected]> |
[Clang][ARM] Define __VFP_FP__ macro unconditionally
Clang only defines __VFP_FP__ when the FPU is enabled. However, gcc defines it unconditionally.
This patch aligns Clang with gcc.
Reviewed By:
[Clang][ARM] Define __VFP_FP__ macro unconditionally
Clang only defines __VFP_FP__ when the FPU is enabled. However, gcc defines it unconditionally.
This patch aligns Clang with gcc.
Reviewed By: peter.smith, rengolin
Differential Revision: https://reviews.llvm.org/D100372
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Revision tags: llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2 |
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c5046ebd |
| 09-Dec-2020 |
Lucas Prates <[email protected]> |
[ARM] Adding v8.7-A command-line support for the ARM target
This extends the command-line support for the 'armv8.7-a' architecture name to the ARM target.
Based on a patch written by Momchil Veliko
[ARM] Adding v8.7-A command-line support for the ARM target
This extends the command-line support for the 'armv8.7-a' architecture name to the ARM target.
Based on a patch written by Momchil Velikov.
Reviewed By: ostannard
Differential Revision: https://reviews.llvm.org/D93231
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Revision tags: llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2 |
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a6fcf5ca |
| 05-Jun-2020 |
Ties Stuij <[email protected]> |
[clang][BFloat] add NEON emitter for bfloat
Summary: This patch adds the bfloat16_t struct typedefs (e.g. bfloat16x8x2_t) to arm_neon.h
This patch is part of a series implementing the Bfloat16 exte
[clang][BFloat] add NEON emitter for bfloat
Summary: This patch adds the bfloat16_t struct typedefs (e.g. bfloat16x8x2_t) to arm_neon.h
This patch is part of a series implementing the Bfloat16 extension of the Armv8.6-a architecture, as detailed here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
The bfloat type, and its properties are specified in the Arm Architecture Reference Manual:
https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
The following people contributed to this patch: - Luke Cheeseman - Simon Tatham - Ties Stuij
Reviewers: t.p.northover, fpetrogalli, sdesmalen, az, LukeGeeson
Reviewed By: fpetrogalli
Subscribers: SjoerdMeijer, LukeGeeson, pbarrio, mgorny, kristof.beyls, ilya-biryukov, MaskRay, jkorous, arphaman, usaxena95, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D79708
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ecd682bb |
| 04-Jun-2020 |
Ties Stuij <[email protected]> |
[ARM] Add __bf16 as new Bfloat16 C Type
Summary: This patch upstreams support for a new storage only bfloat16 C type. This type is used to implement primitive support for bfloat16 data, in line with
[ARM] Add __bf16 as new Bfloat16 C Type
Summary: This patch upstreams support for a new storage only bfloat16 C type. This type is used to implement primitive support for bfloat16 data, in line with the Bfloat16 extension of the Armv8.6-a architecture, as detailed here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
The bfloat type, and its properties are specified in the Arm Architecture Reference Manual:
https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
In detail this patch: - introduces an opaque, storage-only C-type __bf16, which introduces a new bfloat IR type.
This is part of a patch series, starting with command-line and Bfloat16 assembly support. The subsequent patches will upstream intrinsics support for BFloat16, followed by Matrix Multiplication and the remaining Virtualization features of the armv8.6-a architecture.
The following people contributed to this patch: - Luke Cheeseman - Momchil Velikov - Alexandros Lamprineas - Luke Geeson - Simon Tatham - Ties Stuij
Reviewers: SjoerdMeijer, rjmccall, rsmith, liutianle, RKSimon, craig.topper, jfb, LukeGeeson, fpetrogalli
Reviewed By: SjoerdMeijer
Subscribers: labrinea, majnemer, asmith, dexonsmith, kristof.beyls, arphaman, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D76077
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8eda7161 |
| 02-Jun-2020 |
Nick Desaulniers <[email protected]> |
[Clang][A32/T32][Linux] -O1 implies -fomit-frame-pointer
Summary: An upgrade of LLVM for CrOS [0] containing [1] triggered a bunch of errors related to writing to reserved registers for a Linux kern
[Clang][A32/T32][Linux] -O1 implies -fomit-frame-pointer
Summary: An upgrade of LLVM for CrOS [0] containing [1] triggered a bunch of errors related to writing to reserved registers for a Linux kernel's arm64 compat vdso (which is a aarch32 image).
After a discussion on LKML [2], it was determined that -f{no-}omit-frame-pointer was not being specified. Comparing GCC and Clang [3], it becomes apparent that GCC defaults to omitting the frame pointer implicitly when optimizations are enabled, and Clang does not. ie. setting -O1 (or above) implies -fomit-frame-pointer. Clang was defaulting to -fno-omit-frame-pointer implicitly unless -fomit-frame-pointer was set explicitly.
Why this becomes a problem is that the Linux kernel's arm64 compat vdso contains code that uses r7. r7 is used sometimes for the frame pointer (for example, when targeting thumb (-mthumb)). See useR7AsFramePointer() in llvm/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.h. This is mostly for legacy/compatibility reasons, and the 2019 Q4 revision of the ARM AAPCS looks to standardize r11 as the frame pointer for aarch32, though this is not yet implemented in LLVM.
Users that are reliant on the implicit value if unspecified when optimizations are enabled should explicitly choose -fomit-frame-pointer (new behavior) or -fno-omit-frame-pointer (old behavior).
[0] https://bugs.chromium.org/p/chromium/issues/detail?id=1084372 [1] https://reviews.llvm.org/D76848 [2] https://lore.kernel.org/lkml/[email protected]/ [3] https://godbolt.org/z/0oY39t
Reviewers: kristof.beyls, psmith, danalbert, srhines, MaskRay, ostannard, efriedma
Reviewed By: psmith, danalbert, srhines, MaskRay, efriedma
Subscribers: efriedma, olista01, MaskRay, vhscampos, cfe-commits, llvm-commits, manojgupta, llozano, glider, hctim, eugenis, pcc, peter.smith, srhines
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D80828
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Revision tags: llvmorg-10.0.1-rc1 |
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| #
7da19051 |
| 09-Apr-2020 |
Luke Geeson <[email protected]> |
[AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics
This patch upstreams support for the Armv8.6-a Matrix Multiplication Extension. A summary of the features can be found here:
https://community.
[AArch32] Armv8.6-a Matrix Mult Assembly + Intrinsics
This patch upstreams support for the Armv8.6-a Matrix Multiplication Extension. A summary of the features can be found here:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
This patch includes:
- Assembly support for AArch32 - Intrinsics Support for AArch32 Neon Intrinsics for Matrix Multiplication
Note: these extensions are optional in the 8.6a architecture and so have to be enabled by default
No additional IR types or C Types are needed for this extension.
This is part of a patch series, starting with BFloat16 support and the other components in the armv8.6a extension (in previous patches linked in phabricator)
Based on work by: - Luke Geeson - Oliver Stannard - Luke Cheeseman
Reviewers: t.p.northover, miyuki
Reviewed By: miyuki
Subscribers: miyuki, ostannard, kristof.beyls, hiraditya, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D77872
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71ae267d |
| 26-Mar-2020 |
Ties Stuij <[email protected]> |
[PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support
Summary: This patch introduces command-line support for the Armv8.6-a architecture and assembly support for BFloat16. Details can be found
[PATCH] [ARM] ARMv8.6-a command-line + BFloat16 Asm Support
Summary: This patch introduces command-line support for the Armv8.6-a architecture and assembly support for BFloat16. Details can be found https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a
in addition to the GCC patch for the 8..6-a CLI: https://gcc.gnu.org/legacy-ml/gcc-patches/2019-11/msg02647.html
In detail this patch
- march options for armv8.6-a - BFloat16 assembly
This is part of a patch series, starting with command-line and Bfloat16 assembly support. The subsequent patches will upstream intrinsics support for BFloat16, followed by Matrix Multiplication and the remaining Virtualization features of the armv8.6-a architecture.
Based on work by: - labrinea - MarkMurrayARM - Luke Cheeseman - Javed Asbar - Mikhail Maltsev - Luke Geeson
Reviewers: SjoerdMeijer, craig.topper, rjmccall, jfb, LukeGeeson
Reviewed By: SjoerdMeijer
Subscribers: stuij, kristof.beyls, hiraditya, dexonsmith, danielkiss, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D76062
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Revision tags: llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4 |
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cdeeb548 |
| 09-Mar-2020 |
Mikhail Maltsev <[email protected]> |
[ARM,CDE] Implement CDE feature test macros
Summary: This patch implements feature test macros for the CDE extension according to the upcoming ACLE specification.
The following 2 macros are being a
[ARM,CDE] Implement CDE feature test macros
Summary: This patch implements feature test macros for the CDE extension according to the upcoming ACLE specification.
The following 2 macros are being added: - __ARM_FEATURE_CDE - defined as '1' when any coprocessor is configured as a CDE coprocessor - __ARM_FEATURE_CDE_COPROC - defined as an 8-bit mask, each bit of the mask corresponds to a coprocessor and is set when the corresponding coprocessor is configured as CDE (and cleared otherwise).
The patch also exposes the value of __ARM_FEATURE_CDE_COPROC in the target-independent method TargetInfo::getARMCDECorpocMask, the method will be used in follow-up patches implementing semantic checks of CDE intrinsics (we want to diagnose the cases when CDE intrinsics are used with coprocessors that are not configured as CDE).
Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM
Reviewed By: simon_tatham
Subscribers: kristof.beyls, danielkiss, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D75843
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Revision tags: llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2 |
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3627c91e |
| 05-Feb-2020 |
Momchil Velikov <[email protected]> |
[ARM][TargetParser] Improve handling of dependencies between target features
The patch at https://reviews.llvm.org/D64048 added "negative" dependency handling in `ARM::appendArchExtFeatures`: featur
[ARM][TargetParser] Improve handling of dependencies between target features
The patch at https://reviews.llvm.org/D64048 added "negative" dependency handling in `ARM::appendArchExtFeatures`: feature "noX" removes all features, which imply "X".
This patch adds the "positive" handling: feature "X" adds all the feature strings implied by "X".
(This patch also comes from the suggestion here https://reviews.llvm.org/D72633#inline-658582)
Differential Revision: https://reviews.llvm.org/D72762
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7128aace |
| 04-Feb-2020 |
Mikhail Maltsev <[email protected]> |
[ARM] Make ARM::ArchExtKind use 64-bit underlying type, NFCI
Summary: This patch changes the underlying type of the ARM::ArchExtKind enumeration to uint64_t and adjusts the related code.
The goal o
[ARM] Make ARM::ArchExtKind use 64-bit underlying type, NFCI
Summary: This patch changes the underlying type of the ARM::ArchExtKind enumeration to uint64_t and adjusts the related code.
The goal of the patch is to prepare the code base for a new architecture extension.
Reviewers: simon_tatham, eli.friedman, ostannard, dmgreen
Reviewed By: dmgreen
Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, llvm-commits, pbarrio
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D73906
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Revision tags: llvmorg-10.0.0-rc1 |
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adcd0268 |
| 28-Jan-2020 |
Benjamin Kramer <[email protected]> |
Make llvm::StringRef to std::string conversions explicit.
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here.
This is mostly m
Make llvm::StringRef to std::string conversions explicit.
This is how it should've been and brings it more in line with std::string_view. There should be no functional change here.
This is mostly mechanical from a custom clang-tidy check, with a lot of manual fixups. It uncovers a lot of minor inefficiencies.
This doesn't actually modify StringRef yet, I'll do that in a follow-up.
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