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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dfcmp.mir79 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
107 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
116 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
143 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
152 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
179 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
188 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
215 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
224 ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
251 ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
[all …]
H A Dstore_4_unaligned.mir42 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
44 ; MIPS32: SWL [[COPY1]], [[ADDiu]], 3 :: (store (s32) into @float_align1, align 1)
45 ; MIPS32: SWR [[COPY1]], [[ADDiu]], 0 :: (store (s32) into @float_align1, align 1)
68 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
69 ; MIPS32: SWC1 [[COPY]], [[ADDiu]], 0 :: (store (s32) into @float_align4)
91 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
92 ; MIPS32: SW [[COPY]], [[ADDiu]], 0 :: (store (s32) into @i32_align8, align 8)
H A Dload_4_unaligned.mir38 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
40 …; MIPS32: [[LWL:%[0-9]+]]:gpr32 = LWL [[ADDiu]], 3, [[DEF]] :: (dereferenceable load (s32) from @f…
41 …; MIPS32: [[LWR:%[0-9]+]]:gpr32 = LWR [[ADDiu]], 0, [[LWL]] :: (dereferenceable load (s32) from @f…
60 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align4
61 …; MIPS32: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float_a…
80 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align8
81 …; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align8, …
H A Dload_4_unaligned_r6.mir39 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
40 …; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float…
60 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
61 …; MIPS32R6: [[LWC1_:%[0-9]+]]:fgr32 = LWC1 [[ADDiu]], 0 :: (dereferenceable load (s32) from @float…
81 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
82 …; MIPS32R6: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (dereferenceable load (s32) from @i32_align2…
H A Dstore_4_unaligned_r6.mir42 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align1
43 ; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store (s32) into @float_align1, align 1)
65 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @float_align8
66 ; MIPS32R6: SWC1 [[COPY]], [[ADDiu]], 0 :: (store (s32) into @float_align8, align 8)
88 ; MIPS32R6: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @i32_align2
89 ; MIPS32R6: SW [[COPY]], [[ADDiu]], 0 :: (store (s32) into @i32_align2, align 2)
H A Dadd.mir48 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], 3
49 ; MIPS32: $v0 = COPY [[ADDiu]]
71 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[COPY]], -3
72 ; MIPS32: $v0 = COPY [[ADDiu]]
H A Dvar_arg.mir61 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
62 ; MIPS32: SW [[COPY1]], [[ADDiu]], 0 :: (store (s32) into %fixed-stack.1)
64 ; MIPS32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.2, 0
67 ; MIPS32: [[ADDiu2:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.3, 0
70 ; MIPS32: [[ADDiu3:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
71 ; MIPS32: [[ADDiu4:%[0-9]+]]:gpr32 = ADDiu %stack.0.fmt.addr, 0
72 ; MIPS32: [[ADDiu5:%[0-9]+]]:gpr32 = ADDiu %stack.1.ap, 0
73 ; MIPS32: [[ADDiu6:%[0-9]+]]:gpr32 = ADDiu %stack.2.aq, 0
74 ; MIPS32: [[ADDiu7:%[0-9]+]]:gpr32 = ADDiu %stack.3.s, 0
H A Dphi.mir152 ; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
153 …; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
154 ; MIPS32FP32: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
177 ; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
178 …; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
179 ; MIPS32FP64: [[ADDiu1:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.1, 0
307 ; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
308 …; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
327 ; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
328 …; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
H A Dgloal_address.mir21 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LUi]], target-flags(mips-abs-lo) @.str
26 ; MIPS32: $a0 = COPY [[ADDiu]]
H A Dconstants.mir54 ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65526
55 ; MIPS32: $v0 = COPY [[ADDiu]]
H A Dselect.mir151 ; MIPS32FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
152 … ; MIPS32FP32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
161 ; MIPS32FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu %fixed-stack.0, 0
162 … ; MIPS32FP64: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from %fixed-stack.0, align 8)
H A Dgloal_address_pic.mir99 … ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LW]], target-flags(mips-abs-lo) @f_with_local_linkage
103 …; MIPS32: JALRPseudo [[ADDiu]], csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implici…
156 …; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu [[LW]], target-flags(mips-abs-lo) @val_with_local_linkage
157 ; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load (s32) from @val_with_local_linkage)
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmacro-aliases.s6 subu $4, $4, 4 # CHECK: ADDiu
8 subu $gp, $gp, 4 # CHECK: ADDiu
10 subu $sp, $sp, 4 # CHECK: ADDiu
12 subu $4, $4, -4 # CHECK: ADDiu
14 subu $gp, $gp, -4 # CHECK: ADDiu
16 subu $sp, $sp, -4 # CHECK: ADDiu
18 subu $sp, $sp, -(4 + 4) # CHECK: ADDiu
21 subu $4, 8 # CHECK: ADDiu
23 subu $gp, 8 # CHECK: ADDiu
25 subu $sp, 8 # CHECK: ADDiu
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/longbranch/
H A Dbranch-limits-fp-mips.mir85 ; MIPS: $v0 = ADDiu $zero, 0
100 ; PIC: $sp = ADDiu $sp, -8
111 ; PIC: $sp = ADDiu $sp, 8
116 ; PIC: $v0 = ADDiu $zero, 0
120 ; PIC: $v0 = ADDiu $zero, 1
131 $v0 = ADDiu $zero, 0
135 $v0 = ADDiu $zero, 1
204 ; PIC: $sp = ADDiu $sp, -8
215 ; PIC: $sp = ADDiu $sp, 8
235 $v0 = ADDiu $zero, 0
[all …]
H A Dbranch-limits-fp-mipsr6.mir85 ; R6: $v0 = ADDiu $zero, 0
89 ; R6: $v0 = ADDiu $zero, 1
100 ; PIC: $sp = ADDiu $sp, -8
109 ; PIC: $sp = ADDiu $sp, 8
129 $v0 = ADDiu $zero, 0
133 $v0 = ADDiu $zero, 1
185 ; R6: $v0 = ADDiu $zero, 0
200 ; PIC: $sp = ADDiu $sp, -8
209 ; PIC: $sp = ADDiu $sp, 8
229 $v0 = ADDiu $zero, 0
[all …]
H A Dbranch-limits-msa.mir331 renamable $v0 = ADDiu $zero, 1
335 renamable $v0 = ADDiu $zero, 0
445 renamable $v0 = ADDiu $zero, 1
449 renamable $v0 = ADDiu $zero, 0
559 renamable $v0 = ADDiu $zero, 1
563 renamable $v0 = ADDiu $zero, 0
670 renamable $v0 = ADDiu $zero, 1
674 renamable $v0 = ADDiu $zero, 0
781 renamable $v0 = ADDiu $zero, 1
785 renamable $v0 = ADDiu $zero, 0
[all …]
H A Dbranch-limits-int-mipsr6.mir196 ; PIC: $sp = ADDiu $sp, -8
205 ; PIC: $sp = ADDiu $sp, 8
283 ; PIC: $sp = ADDiu $sp, -8
292 ; PIC: $sp = ADDiu $sp, 8
370 ; PIC: $sp = ADDiu $sp, -8
379 ; PIC: $sp = ADDiu $sp, 8
466 ; PIC: $sp = ADDiu $sp, 8
553 ; PIC: $sp = ADDiu $sp, 8
640 ; PIC: $sp = ADDiu $sp, 8
727 ; PIC: $sp = ADDiu $sp, 8
[all …]
H A Dbranch-limits-int-micromipsr6.mir196 ; PIC: $sp = ADDiu $sp, -8
205 ; PIC: $sp = ADDiu $sp, 8
283 ; PIC: $sp = ADDiu $sp, -8
292 ; PIC: $sp = ADDiu $sp, 8
370 ; PIC: $sp = ADDiu $sp, -8
379 ; PIC: $sp = ADDiu $sp, 8
466 ; PIC: $sp = ADDiu $sp, 8
553 ; PIC: $sp = ADDiu $sp, 8
640 ; PIC: $sp = ADDiu $sp, 8
727 ; PIC: $sp = ADDiu $sp, 8
[all …]
H A Dbranch-limits-int-microMIPS.mir154 ; PIC: $sp = ADDiu $sp, -8
165 ; PIC: $sp = ADDiu $sp, 8
249 ; PIC: $sp = ADDiu $sp, -8
260 ; PIC: $sp = ADDiu $sp, 8
344 ; PIC: $sp = ADDiu $sp, -8
355 ; PIC: $sp = ADDiu $sp, 8
439 ; PIC: $sp = ADDiu $sp, -8
534 ; PIC: $sp = ADDiu $sp, -8
625 ; PIC: $sp = ADDiu $sp, -8
720 ; PIC: $sp = ADDiu $sp, -8
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
61 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); in GetInstSeqLs()
92 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi()
134 ADDiu = Mips::ADDiu; in Analyze()
139 ADDiu = Mips::DADDiu; in Analyze()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dmicromips-eva.mir102 %1:gpr32 = ADDiu killed %0, target-flags(mips-abs-lo) @bArray
104 %3:gpr32 = ADDiu killed %2, -7
107 %5:gpr32 = ADDiu killed %4, -7
110 %7:gpr32 = ADDiu killed %6, target-flags(mips-abs-lo) @hArray
112 %9:gpr32 = ADDiu killed %8, -7
115 %11:gpr32 = ADDiu killed %10, -7
118 %13:gpr32 = ADDiu killed %12, target-flags(mips-abs-lo) @wArray
120 %15:gpr32 = ADDiu killed %14, -7
179 %3:gpr32 = ADDiu $zero, 42
191 %5:gpr32 = ADDiu killed %4, 42
H A Dshrink-wrap-buildpairf64-extractelementf64.mir71 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
87 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
135 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
151 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/micromips-sizereduction/
H A Dmicromips-no-lwp-swp.mir60 $sp = ADDiu $sp, -24
71 $sp = ADDiu $sp, 24
119 $sp = ADDiu $sp, -24
130 $sp = ADDiu $sp, 24
178 $sp = ADDiu $sp, -24
189 $sp = ADDiu $sp, 24
237 $sp = ADDiu $sp, -24
248 $sp = ADDiu $sp, 24
H A Dmicromips-lwp-swp.mir65 $sp = ADDiu $sp, -32
81 $sp = ADDiu $sp, 32
133 $sp = ADDiu $sp, -32
149 $sp = ADDiu $sp, 32
201 $sp = ADDiu $sp, -32
217 $sp = ADDiu $sp, 32
269 $sp = ADDiu $sp, -32
285 $sp = ADDiu $sp, 32
/llvm-project-15.0.7/llvm/test/DebugInfo/MIR/Mips/
H A Ddbg-call-site-param-addiu.mir17 ## Check that parameters value loaded by instruction ADDiu/DADDiu is
109 $sp = ADDiu $sp, -24
119 renamable $a2 = nsw ADDiu renamable $s0, 10, debug-location !18
120 $a0 = ADDiu $zero, 44, debug-location !18
126 renamable $v1 = nsw ADDiu renamable $v0, 10, debug-location !18
131 $sp = ADDiu $sp, 24

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