Searched refs:ADD_LO (Results 1 – 6 of 6) sorted by relevance
| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | early-if-convert-cost.ll | 10 ; GCN: v_add_f64 v[[[ADD_LO:[0-9]+]]:[[ADD_HI:[0-9]+]]], v[[[VAL_LO]]:[[VAL_HI]]], v[[[VAL_LO]]:[[V…
11 ; GCN-DAG: v_cndmask_b32_e32 v[[RESULT_LO:[0-9]+]], v[[ADD_LO]], v[[VAL_LO]], vcc
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| H A D | add.v2i16.ll | 183 ; VI: v_add_u16_e32 v[[ADD_LO:[0-9]+]], v[[A]], v[[B]]
187 ; VI: buffer_store_dwordx2 v[[[ADD_LO]]:[[ADD_HI]]]
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 46 ADD_LO, enumerator
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| H A D | RISCVISelDAGToDAG.cpp | 1864 if (Addr.getOpcode() == RISCVISD::ADD_LO) { in SelectAddrRegImm()
1874 if (Base.getOpcode() == RISCVISD::ADD_LO) { in SelectAddrRegImm()
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| H A D | RISCVInstrInfo.td | 86 def riscv_add_lo : SDNode<"RISCVISD::ADD_LO", SDTIntBinOp>;
1229 /// HI and ADD_LO address nodes.
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| H A D | RISCVISelLowering.cpp | 3735 return DAG.getNode(RISCVISD::ADD_LO, DL, Ty, MNHi, AddrLo); in getAddr()
3820 return DAG.getNode(RISCVISD::ADD_LO, DL, Ty, MNAdd, AddrLo); in getStaticTLSAddr()
9750 if (Ptr.getOpcode() != RISCVISD::ADD_LO || in getTargetConstantFromLoad()
11612 NODE_NAME_CASE(ADD_LO) in getTargetNodeName()
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