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/llvm-project-15.0.7/llvm/test/tools/llvm-remark-size-diff/
H A Djson-add-remove-func.test7 ; ADD-LABEL: "Files":
14 ; ADD-NEXT: 1,
15 ; ADD-NEXT: 1
16 ; ADD-NEXT: ],
18 ; ADD-NEXT: 1,
19 ; ADD-NEXT: 1
26 ; ADD-NEXT: 0,
27 ; ADD-NEXT: 1
28 ; ADD-NEXT: ],
30 ; ADD-NEXT: 0,
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/GVN/PRE/
H A Dphi-translate-add.ll8 ; ADD-TRANS-ON-LABEL: @phi_translation_hoists_add(
9 ; ADD-TRANS-ON-NEXT: entry:
14 ; ADD-TRANS-ON: for.body:
17 ; ADD-TRANS-ON: exit:
18 ; ADD-TRANS-ON-NEXT: ret double [[LOAD_PRE]]
21 ; ADD-TRANS-OFF-NEXT: entry:
23 ; ADD-TRANS-OFF: for.body:
24 ; ADD-TRANS-OFF-NEXT: [[ADD:%.*]] = add nuw nsw i64 [[IDX:%.*]], 1
25 ; ADD-TRANS-OFF-NEXT: [[GEP:%.*]] = getelementptr inbounds double, ptr [[A:%.*]], i64 [[ADD]]
29 ; ADD-TRANS-OFF: exit:
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dexecute-only-big-stack-frame.ll4 ; RUN: | FileCheck --check-prefix=CHECK-MOVW-MOVT-ADD %s
22 ; CHECK-MOVW-MOVT-ADD-LABEL: test_big_stack_frame:
23 ; CHECK-MOVW-MOVT-ADD-NOT: ldr {{r[0-9]+}}, .{{.*}}
25 ; CHECK-MOVW-MOVT-ADD: movt [[REG1]], #65535
26 ; CHECK-MOVW-MOVT-ADD: add sp, [[REG1]]
29 ; CHECK-MOVW-MOVT-ADD: movt [[REG2]], #0
30 ; CHECK-MOVW-MOVT-ADD: add [[REG2]], sp
33 ; CHECK-MOVW-MOVT-ADD: movt [[REG3]], #0
34 ; CHECK-MOVW-MOVT-ADD: add [[REG3]], sp
37 ; CHECK-MOVW-MOVT-ADD: movt [[REG4]], #1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dslow-incdec.ll12 ; ADD-LABEL: inc:
13 ; ADD: # %bb.0:
15 ; ADD-NEXT: addl $1, %eax
16 ; ADD-NEXT: retl
28 ; ADD-LABEL: dec:
29 ; ADD: # %bb.0:
32 ; ADD-NEXT: retl
99 ; ADD-NEXT: retl
142 ; ADD-NEXT: setne %al
143 ; ADD-NEXT: addb $1, a
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/COFF/
H A Dadd-section.test9 # CHECK-ADD: SectionCount: 2
10 # CHECK-ADD: Name: .text
11 # CHECK-ADD: Name: .test.section
12 # CHECK-ADD: Characteristics [
13 # CHECK-ADD-NEXT: IMAGE_SCN_ALIGN_1BYTES
15 # CHECK-ADD-NEXT: ]
16 # CHECK-ADD: SectionData (
18 # CHECK-ADD-NEXT: )
25 # CHECK-ADD-EMPTY-NAME: Name: .text
30 # CHECK-ADD-EMPTY-NAME-NEXT: ]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfadd.ll6 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W
26 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
27 ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
44 ; R600: ADD
45 ; R600: ADD
46 ; R600: ADD
47 ; R600: ADD
48 ; R600: ADD
49 ; R600: ADD
50 ; R600: ADD
[all …]
H A Dadd.i16.ll7 ; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
8 ; VI-NEXT: buffer_store_short [[ADD]]
24 ; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0x7b, [[A]]
25 ; VI-NEXT: buffer_store_short [[ADD]]
39 ; VI: v_add_u16_e32 [[ADD:v[0-9]+]], 0xfcb3, [[A]]
40 ; VI-NEXT: buffer_store_short [[ADD]]
54 ; VI: v_add_u16_e32 [[ADD:v[0-9]+]], -1, [[A]]
55 ; VI-NEXT: buffer_store_short [[ADD]]
70 ; VI: v_add_u16_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
71 ; VI-NEXT: buffer_store_dword [[ADD]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dextractelement.ll13 ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP2]], [[TMP3]]
14 ; CHECK-NEXT: ret float [[ADD]]
21 ; THRESH1-NEXT: ret float [[ADD]]
28 ; THRESH2-NEXT: ret float [[ADD]]
44 ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[X0X0]], [[X1X1]]
45 ; CHECK-NEXT: store float [[ADD]], float* @a, align 4
54 ; THRESH1-NEXT: store float [[ADD]], float* @a, align 4
63 ; THRESH2-NEXT: store float [[ADD]], float* @a, align 4
82 ; CHECK-NEXT: ret float [[ADD]]
92 ; THRESH1-NEXT: ret float [[ADD]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-add-v256.mir45 ; SSE2: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV2]]
55 ; AVX1: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV2]]
63 ; AVX2: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[DEF]], [[DEF1]]
64 ; AVX2: $ymm0 = COPY [[ADD]](<32 x s8>)
90 ; SSE2: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV2]]
100 ; AVX1: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV2]]
109 ; AVX2: $ymm0 = COPY [[ADD]](<16 x s16>)
135 ; SSE2: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV2]]
145 ; AVX1: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV2]]
154 ; AVX2: $ymm0 = COPY [[ADD]](<8 x s32>)
[all …]
H A Dlegalize-add-v512.mir49 ; AVX1: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV4]]
70 ; AVX512BW: $zmm0 = COPY [[ADD]](<64 x s8>)
96 ; AVX1: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV4]]
117 ; AVX512BW: $zmm0 = COPY [[ADD]](<32 x s16>)
143 ; AVX1: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV4]]
154 ; AVX512F: $zmm0 = COPY [[ADD]](<16 x s32>)
160 ; AVX512BW: $zmm0 = COPY [[ADD]](<16 x s32>)
186 ; AVX1: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV4]]
197 ; AVX512F: $zmm0 = COPY [[ADD]](<8 x s64>)
203 ; AVX512BW: $zmm0 = COPY [[ADD]](<8 x s64>)
[all …]
H A Dlegalize-add.mir37 ; X64: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
38 ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
45 ; X32: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
46 ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
70 ; X64: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
71 ; X64: $eax = COPY [[ADD]](s32)
76 ; X32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
77 ; X32: $eax = COPY [[ADD]](s32)
100 ; X64: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
101 ; X64: $rax = COPY [[ADD]](s64)
H A Dlegalize-add-v128.mir41 ; ALL: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
42 ; ALL: $xmm0 = COPY [[ADD]](<16 x s8>)
67 ; ALL: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
68 ; ALL: $xmm0 = COPY [[ADD]](<8 x s16>)
93 ; ALL: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
94 ; ALL: $xmm0 = COPY [[ADD]](<4 x s32>)
119 ; ALL: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
120 ; ALL: $xmm0 = COPY [[ADD]](<2 x s64>)
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Ddont-recompute.ll33 ; CHECK-NEXT: [[ADD]] = add i32 [[A_05]], [[M:%.*]]
34 ; CHECK-NEXT: tail call void @func(i32 [[ADD]])
67 ; CHECK-NEXT: [[ADD]] = add i32 [[A_05]], [[M:%.*]]
68 ; CHECK-NEXT: tail call void @func(i32 [[ADD]])
99 ; CHECK-NEXT: [[ADD]] = add i32 [[A_05]], [[M:%.*]]
100 ; CHECK-NEXT: tail call void @func(i32 [[ADD]])
139 ; CHECK-NEXT: [[ADD]] = add i32 [[A_05]], [[M:%.*]]
140 ; CHECK-NEXT: tail call void @func(i32 [[ADD]])
175 ; CHECK-NEXT: [[ADD]] = add i32 [[A_05]], [[M:%.*]]
176 ; CHECK-NEXT: [[SOFT_USE:%.*]] = add i32 [[ADD]], 123
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/ELF/
H A Dshared-strtab-shstrtab.s75 # SECTION-ADD: Sections [
77 # SECTION-ADD: Name: .foo (
78 # SECTION-ADD: Name: .bar (
79 # SECTION-ADD: Symbols [
80 # SECTION-ADD: Name: foo (
87 # SYMBOL-ADD: Sections [
88 # SYMBOL-ADD: Name: .strtab (
89 # SYMBOL-ADD: Name: .foo (
90 # SYMBOL-ADD: Symbols [
91 # SYMBOL-ADD: Name: foo (
[all …]
H A Dchange-entry-point.test14 # RUN: llvm-readobj --file-headers %t6 | FileCheck %s --check-prefix=ADD
16 # RUN: llvm-readobj --file-headers %t7 | FileCheck %s --check-prefix=ADD-LARGE
20 # RUN: llvm-readobj --file-headers %t9 | FileCheck %s --check-prefix=ADD-UNDERFLOW
23 # RUN: not llvm-objcopy --change-start -xyz %t %t11 2>&1 | FileCheck %s --check-prefix=ADD-ERR
53 # ADD: Entry: 0x1150
57 # ADD-LARGE: Entry: 0x100001100
58 # ADD-ERR: error: bad entry point increment: '-xyz'
59 # ADD-UNDERFLOW: Entry: 0xFFFFFFFFFFFFFFFF
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-combines.mir23 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
24 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
47 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
48 ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
68 ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
69 ; CHECK: $x0 = COPY [[ADD]](s64)
86 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
87 ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
109 ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
110 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
[all …]
H A Dlegalize-saddsat.mir20 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASHR]], [[C1]]
23 ; CHECK-NEXT: %saddsat:_(s32) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
48 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[C1]]
51 ; CHECK-NEXT: %saddsat:_(s64) = G_SELECT [[AND]](s32), [[ADD]], [[SADDO]]
76 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
78 ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 16
113 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
115 ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 1
149 ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
151 ; CHECK-NEXT: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ADD]], 3
[all …]
/llvm-project-15.0.7/llvm/test/Instrumentation/PoisonChecking/
H A Dub-checks.ll12 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1
29 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1
46 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1
63 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1
80 ; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[A]], 1
83 ; CHECK-NEXT: [[RES:%.*]] = udiv i32 2048, [[ADD]]
95 ; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[A]], 1
98 ; CHECK-NEXT: [[RES:%.*]] = sdiv i32 2048, [[ADD]]
110 ; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[A]], 1
113 ; CHECK-NEXT: [[RES:%.*]] = urem i32 2048, [[ADD]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dselect-optimize-multiple.mir74 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
75 ; RV32I-NEXT: $x10 = COPY [[ADD]]
102 ; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
130 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
158 ; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
170 %10:gpr = ADD %7, killed %9
224 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
248 ; RV32IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
272 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
296 ; RV64IBT-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[PHI]], killed [[PHI1]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dadd2.ll250 ; CHECK-NEXT: ret i16 [[ADD]]
261 ; CHECK-NEXT: ret i16 [[ADD]]
272 ; CHECK-NEXT: ret i16 [[ADD]]
284 ; CHECK-NEXT: ret i32 [[ADD]]
305 ; CHECK-NEXT: ret i16 [[ADD]]
316 ; CHECK-NEXT: ret i16 [[ADD]]
374 ; CHECK-NEXT: ret i32 [[ADD]]
385 ; CHECK-NEXT: ret i32 [[ADD]]
396 ; CHECK-NEXT: ret i32 [[ADD]]
407 ; CHECK-NEXT: ret i32 [[ADD]]
[all …]
H A Dicmp-topbitssame.ll10 ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD:%.*]], 128
24 ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD:%.*]], 128
38 ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD:%.*]], -128
96 ; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[ADD:%.*]], 8
113 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 7
130 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8
147 ; CHECK-NEXT: [[SH:%.*]] = lshr i64 [[ADD:%.*]], 32
168 ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD]], 128
184 ; CHECK-NEXT: [[SH:%.*]] = lshr i16 [[ADD:%.*]], 8
186 ; CHECK-NEXT: [[TMP1:%.*]] = add i16 [[ADD]], 128
[all …]
/llvm-project-15.0.7/clang/test/Index/
H A Dcomplete-super.m43 // RUN: c-index-test -code-completion-at=%s:20:4 %s | FileCheck -check-prefix=CHECK-ADD-RECEIVER %s
44 // CHECK-ADD-RECEIVER: ObjCInstanceMethodDecl:{ResultType void}{TypedText super}{HorizontalSpace }…
50 // RUN: c-index-test -code-completion-at=%s:20:10 %s | FileCheck -check-prefix=CHECK-ADD-ADD %s
51 // CHECK-ADD-ADD: ObjCInstanceMethodDecl:{ResultType void}{TypedText add:}{Placeholder a}{Horizonta…
52 // CHECK-ADD-ADD-NOT: add
53 // CHECK-ADD-ADD: ObjCInstanceMethodDecl:{ResultType void}{TypedText last} (35)
60 // RUN: c-index-test -code-completion-at=%s:20:16 %s | FileCheck -check-prefix=CHECK-ADD-TO %s
61 // CHECK-ADD-TO: ObjCInstanceMethodDecl:{ResultType void}{Informative add:}{TypedText to:}{Placehol…
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-extract-vector-elt.mir354 ; WAVE64-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[SHL]], [[C]]
367 ; WAVE32-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[SHL]], [[C]]
576 ; WAVE64-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
632 ; WAVE32-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
705 ; WAVE64-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
761 ; WAVE32-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
834 ; WAVE64-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
890 ; WAVE32-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
963 ; WAVE64-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
1004 ; WAVE32-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY1]], [[COPY2]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dadd.mir29 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
30 ; MIPS32: $v0 = COPY [[ADD]](s32)
51 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
53 ; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C]](s32)
79 ; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[COPY]]
81 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
107 ; MIPS32: $v0 = COPY [[ADD]](s32)
161 ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
187 ; MIPS32: $v0 = COPY [[ADD]](s32)
220 ; MIPS32: $v1 = COPY [[ADD]](s32)
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dwrapping.ll6 ; CHECK-NEXT: [[ADD:%.*]] = add i16 [[A:%.*]], [[B:%.*]]
7 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[ADD]], 1
21 ; CHECK-NEXT: [[ADD:%.*]] = sub i16 [[A:%.*]], [[B:%.*]]
22 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[ADD]], 1
37 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[ADD]], 1
52 ; CHECK-NEXT: [[OR:%.*]] = or i16 [[ADD]], 1
92 ; CHECK-NEXT: [[ADD:%.*]] = add i8 [[A:%.*]], 1
106 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], -2
107 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ADD]], -2
120 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP1]], -1
[all …]

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