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Searched refs:umc (Results 1 – 24 of 24) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
136 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
140 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
289 if (!adev->umc.ras) in amdgpu_umc_ras_sw_init()
292 ras = adev->umc.ras; in amdgpu_umc_ras_sw_init()
332 if (adev->umc.ras && in amdgpu_umc_ras_late_init()
407 adev->umc.active_mask, adev->umc.umc_inst_num); in amdgpu_umc_loop_all_aid()
409 adev->umc.node_inst_num * adev->umc.umc_inst_num) { in amdgpu_umc_loop_all_aid()
501 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) in amdgpu_umc_pages_in_a_row()
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H A Dumc_v8_10.c216 adev->umc.channel_idx_tbl[node_inst * adev->umc.umc_inst_num * in umc_v8_10_convert_error_address()
217 adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
218 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_convert_error_address()
343 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_correctable_error_count()
344 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()
345 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_correctable_error_count()
362 eccinfo_table_idx = node_inst * adev->umc.umc_inst_num * in umc_v8_10_ecc_info_query_uncorrectable_error_count()
363 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()
364 umc_inst * adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_uncorrectable_error_count()
411 adev->umc.channel_inst_num + in umc_v8_10_ecc_info_query_error_address()
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H A Dumc_v6_7.c50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v6_7_reg_offset()
57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst; in get_umc_v6_7_reg_offset()
106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_correctable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_ecc_info_query_correctable_error_count()
148 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
195 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_convert_error_address()
231 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v6_7_ecc_info_query_error_address()
319 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v6_7_query_correctable_error_count()
H A Damdgpu_umc.h45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst…
46 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_i…
50 for_each_set_bit((node_inst), &(adev->umc.active_mask), adev->umc.node_inst_num)
172 uint64_t err_addr, uint32_t ch, uint32_t umc,
H A Dgmc_v9_0.c1466 adev->umc.funcs = &umc_v6_0_funcs; in gmc_v9_0_set_umc_funcs()
1473 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()
1475 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1482 adev->umc.retire_unit = 1; in gmc_v9_0_set_umc_funcs()
1484 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1487 adev->umc.max_ras_err_cnt_per_query = in gmc_v9_0_set_umc_funcs()
1494 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1502 adev->umc.max_ras_err_cnt_per_query = in gmc_v9_0_set_umc_funcs()
1510 adev->umc.ras = &umc_v12_0_ras; in gmc_v9_0_set_umc_funcs()
2456 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v9_0_hw_init()
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H A Dgmc_v11_0.c552 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
553 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; in gmc_v11_0_set_umc_funcs()
554 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); in gmc_v11_0_set_umc_funcs()
555 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; in gmc_v11_0_set_umc_funcs()
556 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; in gmc_v11_0_set_umc_funcs()
557 if (adev->umc.node_inst_num == 4) in gmc_v11_0_set_umc_funcs()
558 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; in gmc_v11_0_set_umc_funcs()
560 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; in gmc_v11_0_set_umc_funcs()
561 adev->umc.ras = &umc_v8_10_ras; in gmc_v11_0_set_umc_funcs()
943 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v11_0_hw_init()
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H A Dumc_v8_7.c47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_v8_7_reg_offset()
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_correctable_error_count()
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; in umc_v8_7_convert_error_address()
139 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst; in umc_v8_7_ecc_info_query_error_address()
H A Dgmc_v10_0.c589 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; in gmc_v10_0_set_umc_funcs()
590 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
591 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; in gmc_v10_0_set_umc_funcs()
592 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; in gmc_v10_0_set_umc_funcs()
593 adev->umc.retire_unit = 1; in gmc_v10_0_set_umc_funcs()
594 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; in gmc_v10_0_set_umc_funcs()
595 adev->umc.ras = &umc_v8_7_ras; in gmc_v10_0_set_umc_funcs()
1018 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v10_0_hw_init()
1019 adev->umc.funcs->init_registers(adev); in gmc_v10_0_hw_init()
H A Dgmc_v12_0.c569 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; in gmc_v12_0_set_umc_funcs()
570 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); in gmc_v12_0_set_umc_funcs()
571 adev->umc.node_inst_num = 0; in gmc_v12_0_set_umc_funcs()
572 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); in gmc_v12_0_set_umc_funcs()
573 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; in gmc_v12_0_set_umc_funcs()
574 adev->umc.ras = &umc_v8_14_ras; in gmc_v12_0_set_umc_funcs()
911 if (adev->umc.funcs && adev->umc.funcs->init_registers) in gmc_v12_0_hw_init()
912 adev->umc.funcs->init_registers(adev); in gmc_v12_0_hw_init()
H A Damdgpu_ras.c1030 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1037 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1041 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()
1045 if (adev->umc.ras && in amdgpu_ras_get_ecc_info()
2758 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) in amdgpu_ras_mca2pa_by_idx()
2778 if (adev->umc.ras && adev->umc.ras->get_die_id_from_pa) in amdgpu_ras_mca2pa()
2795 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) in amdgpu_ras_mca2pa()
2890 adev->umc.retire_unit); in __amdgpu_ras_convert_rec_from_rom()
3039 if (adev->umc.ras && adev->umc.ras->convert_ras_err_addr) { in amdgpu_ras_load_bad_pages()
3460 if (!adev->umc.ras || !adev->umc.ras->convert_ras_err_addr) in amdgpu_ras_init_badpage_info()
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H A Dumc_v8_14.h32 #define UMC_V8_14_UMC_INSTANCE_NUM(adev) ((adev)->umc.node_inst_num)
H A Dumc_v6_1.c91 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; in get_umc_6_reg_offset()
303 …uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst… in umc_v6_1_query_error_address()
H A Dumc_v8_14.c34 return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst; in get_umc_v8_14_reg_offset()
H A Dumc_v12_0.c39 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst; in get_umc_v12_0_reg_offset()
45 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst + in get_umc_v12_0_reg_offset()
H A Damdgpu_mca.c33 if (adev->umc.ras->check_ecc_err_status) in amdgpu_mca_is_deferred_error()
34 return adev->umc.ras->check_ecc_err_status(adev, in amdgpu_mca_is_deferred_error()
H A Damdgpu_ras_eeprom.c741 control->ras_num_mca_recs * adev->umc.retire_unit; in amdgpu_ras_eeprom_append_table()
1429 control->ras_num_mca_recs * adev->umc.retire_unit; in amdgpu_ras_eeprom_check()
H A Damdgpu_discovery.c766 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & in amdgpu_discovery_read_from_harvest_table()
1430 adev->umc.node_inst_num++; in amdgpu_discovery_reg_base_init()
H A Damdgpu.h1068 struct amdgpu_umc umc; member
H A Damdgpu_psp.c1867 ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; in psp_ras_initialize()
/linux-6.15/drivers/edac/
H A Damd64_edac.c1347 umc = &pvt->umc[i]; in umc_dump_misc_regs()
1425 int umc; in umc_prep_chip_selects() local
1545 umc = &pvt->umc[i]; in umc_determine_memory_type()
2913 umc = &pvt->umc[i]; in umc_read_mc_regs()
3101 dimm->mtype = pvt->umc[umc].dram_type; in umc_init_csrows()
3368 umc = &pvt->umc[i]; in umc_ecc_enabled()
3540 umc = &pvt->umc[i]; in gpu_dump_misc_regs()
3629 umc *= 2; in gpu_get_umc_base()
3632 umc++; in gpu_get_umc_base()
3646 umc = &pvt->umc[i]; in gpu_read_mc_regs()
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H A Damd64_edac.h382 struct amd64_umc *umc; /* UMC registers */ member
/linux-6.15/drivers/ras/amd/atl/
H A DMakefile16 amd_atl-y += umc.o
/linux-6.15/arch/x86/kernel/cpu/
H A DMakefile45 obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
/linux-6.15/drivers/scsi/
H A Dmegaraid.c3500 megacmd_t __user *umc; in mega_n_to_m() local
3520 umc = MBOX_P(uiocp); in mega_n_to_m()
3522 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()
3537 umc = (megacmd_t __user *)uioc_mimd->mbox; in mega_n_to_m()
3539 if (get_user(upthru, (mega_passthru __user * __user *)&umc->xferaddr)) in mega_n_to_m()